View S3C2400_413840.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
INTRODUCTION
SAMSUNG's S3C2400 16/32-bit RISC microprocessor is designed to provide a cost-effective, low power, small die size and high performance micro-controller solution for hand-held devices and general applications. To reduce total system cost, S3C2400 also provides the following: separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD controller (STN & TFT), 2-channel UART with handshake, 4-channel DMA, System Manager (chip select logic, EDO/SDRAM controller), 4-channel Timers with PWM, I/O Ports, RTC, 8channel 10-bit ADC, IIC-BUS interface, IIS-BUS interface, USB Host, USB Device, Multi-Media Card Interface, SPI and PLL for clock generation. The S3C2400 was developed using an ARM920T core, 0.18um CMOS standard cells and a memory complier. Its low-power, simple, elegant and fully static design is particularly suitable for cost-sensitive and power sensitive applications. Also S3C2400 adopts a new bus architecture, AMBA (Advanced Microcontroller Bus Architecture) An outstanding feature of the S3C2400 is its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with a 8-word line length. By providing complete set of common system peripherals, the S3C2400 minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include: * * * * * * * * * * * * * * * 1.8V internal, 3.3V external (I/O boundary) microprocessor with 16KB I-Cache, 16KB D-Cache, and MMU. External memory controller. (EDO/SDRAM Control, Chip Select logic) LCD controller (up to 4K color STN and 64K color TFT) with 1-ch LCD-dedicated DMA. 4-ch DMAs with external request pins 2-ch UART with handshake (IrDA1.0, 16-byte FIFO)/1-ch SPI 1-ch multi-master IIC-BUS/1-ch IIS-BUS controller MMC interface (ver 2.11) 2-port USB Host /1- port USB Device (ver 1.1) 4-ch PWM timers & 1-ch internal timer Watch Dog Timer 90-bit general purpose I/O ports/8-ch external interrupt source Power control: Normal, Slow, Idle, Stop and SL_IDLE mode 8-ch 10-bit ADC. RTC with calendar function. On-chip clock generator with PLL
1-1
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
FEATURES
Architecture * * * * Integrated system for hand-held devices and general embedded applications. 16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core. Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux. Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance. ARM920T CPU core supports the ARM debug architecture and has a Tracking ICE mode. Internal AMBA(Advanced Microcontroller Bus Architecture) (AMBA2.0, AHB/APB) Cache Memory * * * * * 64 way set-associative cache with I-Cache(16KB) and D-Cache(16KB). 8-words per line with one valid bit and two dirty bits per line Pseudo random or round robin replacement algorithm. Write through or write back cache operation to update the main memory. The write buffer can hold 16 words of data and four address.
* *
Clock & Power Manager * * Low power The on-chip MPLL and UPLL UPLL makes the clock for operating USB Host/Device. MPLL makes the clock for operating MCU at maximum 150Mhz @ 1.8V. Clock can be fed selectively to each function block by software. Power mode: Normal, Slow, Idle, Stop mode and SL_IDLE mode. Normal mode: Normal operating mode. Slow mode: Low frequency clock without PLL. Idle mode: Stop the clock for only CPU. Stop mode: All clocks are stopped. SL_IDLE mode: All clocks except LCD are stopped. Wake up by EINT[7:0] or RTC alarm interrupt from Stop mode.
System Manager * * * * * * Little/Big Endian support. Address space: 32M bytes for each bank (Total 256Mbyte) Supports programmable 8/16/32-bit data bus width for each bank. Fixed bank start address and programmable bank size for 7 banks. Programmable bank start address and bank size for one bank. 8 memory banks. -- 6 memory banks for ROM, SRAM etc. -- 2 memory banks for ROM/SRAM/DRAM(EDO or Synchronous DRAM) Fully Programmable access cycles for all memory banks. Supports external wait signal to expend the bus cycle. Supports self-refresh mode in DRAM/SDRAM for power-down. Supports asymmetric/symmetric address of DRAM. * *
*
* * * *
Interrupt Controller * 32 Interrupt sources (Watch dog timer, 5Timer, 6UART, 8External interrupts, 4 DMA, 2 RTC, 1 ADC, 1 IIC, 1 SPI, 1 MMC, 2 USB) Level/Edge mode on external interrupt source. Programmable polarity of edge and level. Supports FIQ (Fast Interrupt request) for very urgent interrupt request.
* * *
1-2
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
Timer with PWM (Pulse Width Modulation) * 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation Programmable duty cycle, frequency, and polarity Dead-zone generation. Supports external clock source.
A/D Converter * * 8-ch multiplexed ADC. Max. 500KSPS and 10-bit Resolution.
* * *
LCD Controller STN LCD displays Feature * Supports 3 types of STN LCD panels ; 4-bit dual scan, 4-bit single scan, 8-bit single scan display type. Supports the monochrome, 4 gray levels, 16gray levels, 256 color and 4096 colors for STN LCD. Supports multiple screen size -- Typical actual screen size: 640x480, 320x240, 160x160 (pixels) -- Maximum virtual screen size (color mode): 4096x1024, 2048x2048, 1024x4096 etc. Supports power saving mode(Enhanced SL_IDLE mode.)
RTC (Real Time Clock) * * * * Full clock feature: msec, sec, min, hour, day, week, month, year. 32.768 KHz operation. Alarm interrupt. Time tick interrupt * * *
General Purpose Input/Output Ports * * 8 external interrupt ports 90 multiplexed input/output ports
TFT (Thin Film Transistor) color displays Feature * * * * Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette color displays for color TFT. Supports 16 bpp non-palette true-color displays for color TFT. Supports maximum 32K (64K using intensity) color TFT at 16 bpp mode. Supports multiple screen size -- Typical actual screen size: 720x240, 320x240, 160x160 (pixels) -- Recommended maximum screen size: 640x480 (8 bpp, 32bit SDRAM @80MHz) -- Maximum virtual screen size (16bpp mode): 2048x1024 etc
UART * * * * * * * 2-channel UART with DMA-based or interruptbased operation Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive Supports H/W handshaking during transmit/receive Programmable baud rate Supports IrDA 1.0 Loop back mode for testing Each channel has internal 16-byte Tx FIFO and 16-byte Rx FIFO.
Watchdog Timer DMA Controller * * * 4-ch DMA controller. Support memory to memory, IO to memory, memory to IO, IO to IO Burst transfer mode to enhance the transfer rate. * * 16-bit Watchdog Timer. Interrupt request or system reset at time-out.
1-3
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
IIC-BUS Interface * * 1-ch Multi-Master IIC-Bus. Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in the standard mode or up to 400 Kbit/s in the fast mode.
MMC Interface * * * Multi-Media Card Protocol version 2.11 compatible 2x16 Bytes FIFO for receive/transmit. DMA-based or interrupt-based operation.
IIS-BUS Interface * * * 1-ch IIS-bus for audio interface with DMA-based operation. Serial, 8/16bit per channel data transfers. Supports IIS format and MSB-justified data format.
SPI Interface * * * Serial Peripheral Interface Protocol version 2.11 compatible 2x8 bits Shift register for receive/transmit. DMA-based or interrupt-based operation.
Operating Voltage Range * * Core: 1.8V I/O: 3.3V
USB Host * * * 2-port USB Host Complies with OHCI Rev. 1.0 Compatible with the USB Specification version 1.1
Operating Frequency * Up to 150 MHz
USB Device * * * 1-port USB Device. 5 Endpoints for USB Device. Compatible with the USB Specification version 1.1
Package * 208 LQFP/208 FBGA
1-4
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
BLOCK DIAGRAM
ARM920T Instruction MMU C13 IV 2A[31:0] ARM9TDMI Processor core (Internal Embedded ICE) DD[31:0] DV 2A[31:0] C13 Data MMU DPA[31:0] Data CACHE (16KB) WriteBack PA Tag RAM WBPA[31:0] DVA[31:0] ID[31:0] AMBA Bus I/F Write Buffer IPA[31:0] InstructionCA CHE (16KB) External Coproc Interface
JTAG
CP15
LCD CONT.
LCD DMA A H B B U S
BUS CONT. Arbitor/Decode
USB Host CONT.
Interrupt CONT.
ExtMaster
Power Management Memory CONT. SRAM/ROM/DRAM/SDRAM
Clock Generator (MPLL) Bridge & DMA(4Ch)
UART 0, 1
I2C
USB Device A P B B U S
I2S
MMC Watchdog Timer BUS CONT. Arbitor/Decode SPI
GPIO
RTC
ADC Timer/PWM 0 ~ 3, 4(Internal)
Figure 1-1. S3C2400 Block Diagram
1-5
S3C2400 RISC MICROPROCESSOR
PIN ASSIGNMENTS
AIN4 AIN5 AIN6 AIN7 VDDA_ADC XTOrtc XTIrtc RTCVDD VDDi_MPLL VSSi_MPLL MPLLCAP VDDi_UPLL VSSi_UPLL UPLLCAP EINT0/GPE0 EINT1/GPE1/nSS EINT2/GPE2/I2SSDI EINT3/GPE3/nCTS1 EINT4/GPE4/nRTS1 EINT5/GPE5/TCLK1 EINT6/GPE6 EINT7/GPE7 N.C nRESET VDDi EXTCLK VSSIO XTOpll XTIpll VDDIO VDDi SCLK VSSi SCKE/GPA10 nWAIT/GPD10 nGCS7:nSCS1:nRAS1 nGCS6:nSCS0:nRAS0 nGCS5/GPA17 nGCS4/GPA16 nGCS3/GPA15 nGCS2/GPA14 VSSIO nGCS1/GPA13 nGCS0 nWE nOE nBE0:nWBE0:DQM0 nBE1:nWBE1:DQM1 nBE2:nWBE2:DQM2 nBE3:nWBE3:DQM3 nCAS3:nSRAS VDDIO
105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
AIN3 AIN2 AIN1 AIN0 Avref VSSA_ADC VSSIO OM0 OM1 OM2 OM3 RXD1/GPF1/IICSDA TXD1/GPF3/IICSCL RXD0/GPF0 TXD0/GPF2 nRTS0/GPF4/nXBACK nCTS0/GPF5/nXBREQ VDDi VSSi DN0 DP0 DN1/PDN0 DP1/PDP0 VD15/GPC15 VD14/GPC14 VSSIO VDDIO VD13/GPC13 VD12/GPC12 VD11/GPC11 VDDi VSSi VD10/GPC10 VD9/GPC9 VD8/GPC8 VD7/GPC7 VD6/GPC6 VD5/GPC5 VD4/GPC4 VSSIO VD3/GPC3 VD2/GPC2 VD1/GPC1 VD0/GPC0 VFRAME/GPD0 VDDi VSSi VM/GPD1 VLINE/GPD2 VCLK/GPD3 LEND/GPD4 VSSIO
VDDIO SPIMOSI/GPG8/IICSCL SPIMISO/GPG7/IICSDA SPICLK/GPG9/MMCCLK MMCCLK/GPG4/I2SSDI MMCCMD/GPG5/IICSDA MMCDAT/GPG6/IICSCL I2SSDO/GPG3/I2SSDI CDCLK/GPG2 I2SSCLK/GPG1 VSSi VDDi I2SLRCK/GPG0 nXDREQ0/GPE10 nXDACK0/GPE8 nXDREQ1/GPE11/nXBREQ nXDACK1/GPE9/nXBACK TCLK0/GPD9 TOUT3/GPD8 TOUT2/GPD7 TOUT1/GPD6 TOUT0/GPD5 TDO TDI TCK TMS nTRST CLKOUT/GPF6 VDDi VSSi VSSIO VDDIO DATA31/GPB15 DATA30/GPB14 DATA29/GPB13 DATA28/GPB12 DATA27/GPB11 DATA26/GPB10/nSS DATA25/GPB9/I2SSDI DATA24/GPB8 DATA23/GPB7 VSSIO DATA22/GPB6/nRTS1 DATA21/GPB5/nCTS1 DATA20/GPB4/RXD1 DATA19/GPB3/TXD1 DATA18/GPB2/TCLK1 DATA17/GPB1/nXBREQ DATA16/GPB0/nXBACK DATA15 DATA14 VSSIO
PRODUCT OVERVIEW
VSSIO nCAS2:nSCAS nCAS1/GPA12 nCAS0/GPA11 ADDR0/GPA0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 VDDIO VSSIO VDDi VSSi ADDR12 ADDR13 ADDR14 ADDR15 ADDR16/GPA1 ADDR17/GPA2 ADDR18/GPA3 ADDR19/GPA4 ADDR20/GPA5 ADDR21/GPA6 ADDR22/GPA7 ADDR23/GPA8 VDDIO VSSIO ADDR24/GPA9 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 VDDi VSSi DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 VDDIO
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Figure 1-2. S3C2400 Pin Assignments (208-LQFP)
S3C2400X01
208-LQFP
1-6
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 BALL PAD A1 CORNER INDICATOR (NO SOLDEER BALL)
BOTTOM VIEW
Figure 1-3. S3C2400 Pin Assignments (208-FBGA)
1-7
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
Table 1-1. 208-Pin LQFP Pin Assignment Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 VSSIO DATA14 DATA15 DATA16/GPB0/nXBACK DATA17/GPB1/nXBREQ DATA18/GPB2/TCLK1 DATA19/GPB3/TXD1 DATA20/GPB4/RXD1 DATA21/GPB5/nCTS1 DATA22/GPB6/nRTS1 VSSIO DATA23/GPB7 DATA24/GPB8 DATA25/GPB9/I2SSDI DATA26/GPB10/nSS DATA27/GPB11 DATA28/GPB12 DATA29/GPB13 DATA30/GPB14 DATA31/GPB15 VDDIO VSSIO VSSi VDDi CLKOUT/GPF6 nTRST TMS TCK TDI TDO TOUT0/GPD5 TOUT1/GPD6 TOUT2/GPD7 Pin Name Default Function VSSIO DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 VSSIO DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 VDDIO VSSIO VSSi VDDi GPF6 nTRST TMS TCK TDI TDO GPD5 GPD6 GPD7 I/O State @BUS REQ. - Hi-z Hi-z Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- - Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- - - - - -/- - - - - - -/- -/- -/-/- I/O State @STOP - Hi-z Hi-z Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- - Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- - - - - -/- - - - - -/- -/- -/-/- I/O State @nRESET P I I I I I I I I I P I I I I I I I I I P P P P I I I I I O I I I I/O Type vss3op phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm vss3op phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm vdd3op vss3op Vss3i vdd1ih_core phbsu50ct8sm phic phic phic phic phot8 phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm
1-8
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
Table 1-1. 208-Pin LQFP Pin Assignment (Continued) Pin Number 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name TOUT3/GPD8 TCLK0/GPD9 nXDACK1/GPE9/ nXBACK nXDREQ1/GPE11/ nXBREQ nXDACK0/GPE8 nXDREQ0/GPE10 I2SLRCK/GPG0 VDDi VSSi I2SSCLK/GPG1 CDCLK/GPG2 I2SSDO/GPG3/I2SSDI MMCDAT/GPG6/IICSCL MMCCMD/GPG5/ IICSDA MMCCLK/GPG4/I2SSDI SPICLK/GPG9/ MMCCLK SPIMISO/GPG7/IICSDA SPIMOSI/GPG8/IICSCL VDDIO VSSIO LEND/GPD4 VCLK/GPD3 VLINE:HSYNC/GPD2 VM:VDEN/GPD1 VSSi VDDi VFRAME:VSYNC/GPD0 VD0/GPC0 VD1/GPC1 VD2/GPC2 VD3/GPC3 Default Function GPD8 GPD9 GPE9 GPE11 GPE8 GPE10 GPG0 VDDi VSSi GPG1 GPG2 GPG3 GPG6 GPG5 GPG4 GPG9 GPG7 GPG8 VDDIO VSSIO GPD4 GPD3 GPD2 GPD1 VSSi VDDi GPD0 GPC0 GPC1 GPC2 GPC3 I/O State @BUS REQ. -/-/- -/- -/-/- -/-/- -/- -/- -/- - - -/- -/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- - - -/- -/- -:-/- -:-/- - - -:-/- -/- -/- -/- -/- I/O State @STOP -/-/- -/- -/-/- -/-/- -/- -/- -/- - - -/- -/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- - - -/- -/- -:-/- -:-/- - - -:-/- -/- -/- -/- -/- I/O State @nRESET I I I I I I I P P I I I I I I I I I P P I I I I P P I I I I I I/O Type phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm vdd1ih_core vss3i phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50cdct8sm phbsu50cdct8sm phbsu50ct8sm phbsu50ct8sm phbsu50cdct8sm phbsu50cdct8sm vdd3op vss3op phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm vss3i vdd1ih_core phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm
1-9
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
65
VSSIO
VSSIO
-
-
P
vss3op
1-10
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
Table 1-1. 208-Pin LQFP Pin Assignment (Continued) Pin Number 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Pin Name VD4/GPC4 VD5/GPC5 VD6/GPC6 VD7/GPC7 VD8/GPC8 VD9/GPC9 VD10/GPC10 VSSi VDDi VD11/GPC11 VD12/GPC12 VD13/GPC13 VDDIO VSSIO VD14/GPC14 VD15/GPC15 DP1/PDP0 DN1/PDN0 DP0 DN0 VSSi VDDi nCTS0/GPF5/nXBREQ nRTS0/GPF4/nXBACK TXD0/GPF2 RXD0/GPF0 TXD1/GPF3/IICSCL RXD1/GPF1/IICSDA OM3 OM2 OM1 OM0 VSSIO VSSA_ADC Default Function GPC4 GPC5 GPC6 GPC7 GPC8 GPC9 GPC10 VSSi VDDi GPC11 GPC12 GPC13 VDDIO VSSIO GPC14 GPC15 PDP0 PDN0 DP0 DN0 VSSi VDDi GPF5 GPF4 GPF2 GPF0 GPF3 GPF1 OM3 OM2 OM1 OM0 VSSIO VSSA_ADC I/O State @BUS REQ. -/- -/- -/- -/- -/- -/- -/- - - -/- -/- -/- - - -/- -/- -/- -/- - - - - -/-/- -/-/- -/- -/- -/-/- -/-/- - - - - - - I/O State @STOP -/- -/- -/- -/- -/- -/- -/- - - -/- -/- -/- - - -/- -/- -/- -/- - - - - -/-/- -/-/- -/- -/- -/-/- -/-/- - - - - - - I/O State @nRESET I I I I I I I P P I I I P P I I AI AI AI AI P P I I I I I I I I I I P P I/O Type phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm vss3i vdd1ih_core phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm vdd3op vss3op phbsu50ct8sm phbsu50ct8sm pbusb pbusb pbusb pbusb vss3i vdd1ih_core phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50cdct8sm phbsu50cdct8sm phic phic phic phic vss3op vss3t_abb
1-11
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
Table 1-1. 208-Pin LQFP Pin Assignment (Continued) Pin Number 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Avref AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDDA_ADC XTOrtc XTIrtc RTCVDD VDDi_MPLL VSSi_MPLL MPLLCAP VDDi_UPLL VSSi_UPLL UPLLCAP EINT0/GPE0 EINT1/GPE1/nSS EINT2/GPE2/I2SSDI EINT3/GPE3/nCTS1 EINT4/GPE4/nRTS1 EINT5/GPE5/TCLK1 EINT6/GPE6 EINT7/GPE7 N.C nRESET VDDi EXTCLK VSSIO XTOpll nRESET VDDi EXTCLK VSSIO XTOpll Pin Name Default Function Avref AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDDA_ADC XTOrtc XTIrtc RTCVDD VDDi_MPLL VSSi_MPLL MPLLCAP VDDi_UPLL VSSi_UPLL UPLLCAP GPE0 GPE1 GPE2 GPE3 GPE4 GPE5 GPE6 GPE7 I/O State @BUS REQ. - - - - - - - - - - - - - - - - - - - -/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- - - - - - - I/O State @STOP - - - - - - - - - - - - - - - - - - - -/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- - - - - - - I/O State @nRESET AI AI AI AI AI AI AI AI AI P AO AI P P P AI P P AI I I I I I I I I - I P I P AO I/O Type phia_abb phia_abb phia_abb phia_abb phia_abb phia_abb phia_abb phia_abb phia_abb vdd3t_abb phgpad_option phgpad_option vdd1ih vdd1ih_core vss3i phgpad_option vdd1ih_core vss3i phgpad_option phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm - phis vdd1ih phic vss3op phsoscm26
1-12
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
Table 1-1. 208-Pin LQFP Pin Assignment (Continued) Pin Number 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 XTIpll VDDIO VDDi SCLK VSSi SCKE/GPA10 nWAIT/GPD10 nGCS7:nSCS1:nRAS1 nGCS6:nSCS0:nRAS0 nGCS5/GPA17 nGCS4/GPA16 nGCS3/GPA15 nGCS2/GPA14 VSSIO nGCS1/GPA13 nGCS0 nWE nOE nBE0:nWBE0:DQM0 Pin Name Default Function XTIpll VDDIO VDDi SCLK VSSi SCKE GPD10 nGCS7 nGCS6 nGCS5 nGCS4 nGCS3 nGCS2 VSSIO nGCS1 nGCS0 nWE nOE DQM0 I/O State @BUS REQ. - - - Hi-z - Hi-z/O -/- Hi-z:Hi-z:Hi-z Hi-z:Hi-z:Hi-z Hi-z/O Hi-z/O Hi-z/O Hi-z/O - Hi-z/O Hi-z Hi-z Hi-z Hi-z:Hi-z:Hi-z I/O State @STOP - - - Low - Low/O -/- High:High:Low High:High:Low Hi-z or Pre/O Hi-z or Pre/O Hi-z or Pre/O Hi-z or Pre/O - Hi-z or Pre/O Hi-z or Pre Hi-z or Pre Hi-z or Pre Hi-z or Pre: Hi-z or Pre: Hi-z or Pre Hi-z or Pre: Hi-z or Pre: Hi-z or Pre Hi-z or Pre: Hi-z or Pre: Hi-z or Pre Hi-z or Pre: Hi-z or Pre: Hi-z or Pre Low:High - - I/O State @nRESET AI P P O(SCLK) P O(H) I O(H) O(H) O(H) O(H) O(H) O(H) P O(H) O(H) O(H) O(H) O(H) I/O Type phsoscm26 vdd3op vdd1ih_core phot12sm vss3i phot8 phbsu50ct8sm phot8 phot8 phot8 phot8 phot8 phot8 vss3op phot8 phot8 phot8 phot8 phot8
152
nBE1:nWBE1:DQM1
DQM1
Hi-z:Hi-z:Hi-z
O(H)
phot8
153
nBE2:nWBE2:DQM2
DQM2
Hi-z:Hi-z:Hi-z
O(H)
phot8
154
nBE3:nWBE3:DQM3
DQM3
Hi-z:Hi-z:Hi-z
O(H)
phot8
155 156 157
nCAS3:nSRAS VDDIO VSSIO
nSRAS VDDIO VSSIO
Hi-z:Hi-z - -
O(H) P P
phot8 vdd3op vss3op
1-13
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
Table 1-1. 208-Pin LQFP Pin Assignment (Continued) Pin Number 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 Pin Name nCAS2:nSCAS nCAS1/GPA12 nCAS0/GPA11 ADDR0/GPA0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 VDDIO VSSIO VDDi VSSi ADDR12 ADDR13 ADDR14 ADDR15 ADDR16/GPA1 ADDR17/GPA2 ADDR18/GPA3 ADDR19/GPA4 ADDR20/GPA5 ADDR21/GPA6 ADDR22/GPA7 ADDR23/GPA8 VDDIO VSSIO Default Function nSCAS nCAS1 nCAS0 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 VDDIO VSSIO VDDi VSSi ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 VDDIO VSSIO I/O State @BUS REQ. Hi-z:Hi-z Hi-z/O Hi-z/O Hi-z/O Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z - - - - Hi-z Hi-z Hi-z Hi-z Hi-z/O Hi-z/O Hi-z/O Hi-z/O Hi-z/O Hi-z/O Hi-z/O Hi-z/O - - I/O State @STOP Low:High Low/O Low/O Hi-z or Pre/O Hi-z or Pre Hi-z or Pre Hi-z or Pre Hi-z or Pre Hi-z or Pre Hi-z or Pre Hi-z or Pre Hi-z or Pre Hi-z or Pre Hi-z or Pre Hi-z or Pre - - - - Hi-z or Pre Hi-z or Pre Hi-z or Pre Hi-z or Pre Hi-z or Pre/O Hi-z or Pre/O Hi-z or Pre/O Hi-z or Pre/O Hi-z or Pre/O Hi-z or Pre/O Hi-z or Pre/O Hi-z or Pre/O - - I/O State @nRESET O(H) O(H) O(H) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) P P P P O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) P P I/O Type phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 vdd3op vss3op vdd1ih_core vss3i phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 vdd3op vss3op
1-14
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
Table 1-1. 208-Pin LQFP Pin Assignment (Continued) Pin Number 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Pin Name ADDR24/GPA9 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 VDDi VSSi DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 VDDIO Default Function ADDR24 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 VDDi VSSi DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 VDDIO I/O State @BUS REQ. Hi-z/O Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z - - Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z - I/O State @STOP Hi-z or Pre/O Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z - - Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z - I/O State @nRESET O(L) I I I I I I I I P P I I I I I I P I/O Type phot8 phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm vdd1ih_core vss3i phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm vdd3op
NOTES: 1. The @BUS REQ. shows the pin states at the external bus, which is used by the other bus master. The @STOP shows the pin states when S3C2400 is in STOP mode. 2. ' - ` mark indicates the unchanged pin state at STOP mode or Bus Request mode. 3. Hi-z or Pre means Hi-z or Previous state and which is determined by the setting of MISCCR register. 4. AI/AO means analog input/output. 5. P, I, and O mean power, input and output respectively. 6. The I/O state @nRESET shows the pin status in the below @nRESET duration.
4FCLK nRESET
@nRESET
FCLK
1-15
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
7.
The below table shows the I/O types and descriptions.
I/O Type vdd1ih, vss3I vdd1ih_core, vss3I vdd3op, vss3op vdd3t_abb, vss3t_abb phic phis pbusb phot8 phob8sm phot12sm phia_abb phgpad_option phsoscm26 phbsu50ct8sm phbsu50ct12sm phbsu50cdct8sm 1.8V Vdd/Vss for internal logic
Descriptions
1.8V Vdd/Vss for internal logic without input driver 3.3V Vdd/Vss for external logic 3.3V Vdd/Vss for analog circuitry input pad, LVCMOS level input pad, LVCMOS schmitt-trigger level USB pad output pad, tri-state, Io=8mA output pad, medium slew rate, Io=8mA output pad, tri-state, medium slew rate, Io=12mA bi-directional analog pad Pad for analog pin Oscillator cell with enable and feedback resistor bi-directional pad, LVCMOS schmit-trigger, 50Kohm pull-up resistor with control, tri-state, Io=8mA bi-directional pad, LVCMOS schmit-trigger, 50Kohm pull-up resistor with control, tri-state, Io=12mA bi-directional pad, LVCMOS schmit-trigger, 50Kohm pull-up resistor with control, tri-state, selectable output pad(open-drain or tri-state), Io=8mA
1-16
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
Table 1-2. 208-Pin FBGA Pin Assignment Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 VSSIO DATA12 DATA9 DATA8 DATA6 DATA2 VSSIO ADDR21/GPA6 ADDR17/GPA2 ADDR13 VDDi ADDR10 ADDR6 ADDR3 ADDR1 ADDR0/GPA0 DATA17/GPB1/nXBREQ DATA14 VDDIO DATA10 VDDi DATA3 DATA0 ADDR22/GPA7 ADDR18/GPA3 ADDR14 VSSi ADDR11 ADDR7 ADDR2 nCAS0/GPA11 nCAS2:nSCAS Pin Name Pin Number C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 Pin Name DATA20/GPB4/RXD1 DATA19/GPB3/TXD1 DATA15 DATA13 DATA11 DATA7 DATA1 ADDR23/GPA8 ADDR19/GPA4 ADDR15 VSSIO ADDR9 ADDR4 nCAS1/GPA12 VDDIO nCAS3:nSRAS DATA23/GPB7 VSSIO DATA21/GPB5/nCTS1 DATA18/GPB2/TCLK1 DATA16/GPB0/nXBACK VSSi DATA4 VDDIO ADDR20/GPA5 ADDR12 VDDIO ADDR5 VSSIO nBE3:nWBE3:DQM3 nBE2:nWBE2:DQM2 nBE1:nWBE1:DQM1
1-17
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
Table 1-2. 208-Pin FBGA Pin Assignment (Continued) Pin Number E1 E2 E3 E4 E7 E8 E9 E10 E13 E14 E15 E16 F1 F2 F3 F4 F13 F14 F15 F16 G1 G2 G3 G4 G5 G12 G13 G14 G15 G16 Pin Name DATA25/GPB9/I2SSDI DATA26/GPB10/nSS DATA24/GPB8 DATA22/GPB6/nRTS1 DATA5 ADDR24/GPA9 ADDR16/GPA1 ADDR8 nBE0:nWBE0:DQM0 nOE nWE nGCS0 DATA29/GPB13 DATA30/GPB14 DATA31/GPB15 DATA27/GPB11 nGCS1/GPA13 nGCS4/GPA16 nGCS3/GPA15 nGCS2/GPA14 VSSIO VSSi VDDi VDDIO DATA28/GPB12 VSSIO nGCS5/GPA17 nWAIT/GPD10 nGCS7:nSCS1:nRAS1 nGCS6:nSCS0:nRAS0 Pin Number H1 H2 H3 H4 H5 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K12 K13 K14 K15 K16 nTRST TMS TCK TDI CLKOUT/GPF6 SCKE/GPA10 VDDIO VDDi SCLK VSSi TDO TOUT0/GPD5 TOUT1/GPD6 TOUT2/GPD7 I2SLRCK/GPG0 EINT7/GPE7 EXTCLK VSSIO XTOpll XTIpll TOUT3/GPD8 TCLK0/GPD9 nXDACK1/GPE9/nXBACK nXDREQ1/GPE11/nXBREQ I2SSCLK/GPG1 EINT0/GPE0 EINT3/GPE3/nCTS1 N.C nRESET VDDi Pin Name
1-18
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
Table 1-2. 208-Pin FBGA Pin Assignment(Continued) Pin Number L1 L2 L3 L4 L13 L14 L15 L16 M1 M2 M3 M4 M7 M8 M9 M10 M13 M14 M15 M16 nXDACK0/GPE8 nXDREQ0/GPE10 VDDi I2SSDO/GPG3/I2SSDI UPLLCAP EINT4/GPE4/nRTS1 EINT5/GPE5/TCLK1 EINT6/GPE6 VSSi CDCLK/GPG2 MMCCMD/GPG5/IICSDA SPIMISO/GPG7/IICSDA VD4/GPC4 VD13/ GPC13 nRTS0/GPF4/nXBACK OM2 RTCVDD VDDi_UPLL EINT1/GPE1/nSS EINT2/GPE2/I2SSDI Pin Name Pin Number N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 Pin Name MMCDAT/GPG6/IICSCL MMCCLK/GPG4/I2SSDI SPIMOSI/GPG8/IICSCL VM:VDEN/GPD1 VD0/GPC0 VD7/ GPC7 VSSi VDDIO DN0 RXD0/GPF0 VSSA_ADC AIN2 VDDA_ADC VSSi_MPLL MPLLCAP VSSi_UPLL SPICLK/GPG9/MMCCLK VDDIO LEND/GPD4 VSSi VD3/GPC3 VD8/ GPC8 VDDi VD15/ GPC15 DP0 nCTS0/GPF5/nXBREQ RXD1/GPF1/IICSDA OM0 AIN1 AIN7 XTIrtc VDDi_MPLL
1-19
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
Table 1-2. 208-Pin FBGA Pin Assignment (Continued) Pin Number R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 VSSIO VCLK/GPD3 VFRAME:VSYNC/GPD0 VD2/GPC2 VD5/ GPC5 VD9/ GPC9 VD12/ GPC12 VD14/ GPC14 DN1/PDN0 VDDi TXD1/GPF3/IICSCL OM1 Avref AIN4 AIN6 XTOrtc Pin Name Pin Number T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Pin Name VLINE:HSYNC/GPD2 VDDi VD1/GPC1 VSSIO VD6/ GPC6 VD10/ GPC10 VD11/ GPC11 VSSIO DP1/PDP0 VSSi TXD0/GPF2 OM3 VSSIO AIN0 AIN3 AIN5
1-20
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
SIGNAL DESCRIPTIONS Table 1-3. S3C2400 Signal Descriptions Signal BUS CONTROLLER OM[1:0] I OM[1:0] sets S3C2400 in the TEST mode, which is used only at fabrication. Also, it determines the bus width of nGCS0. The logic level is determined by the pull-up/down resistor during the RESET cycle. 00:8-bit ADDR[24:0] DATA[31:0] nGCS[7:0] O IO O 01:16-bit 10:32-bit 11:Test mode I/O Description
ADDR[24:0] (Address Bus) outputs the memory address of the corresponding bank . DATA[31:0] (Data Bus) inputs data during memory read and outputs data during memory write. The bus width is programmable among 8/16/32-bit. nGCS[7:0] (General Chip Select) are activated when the address of a memory is within the address region of each bank. The number of access cycles and the bank size can be programmed. nWE (Write Enable) indicates that the current bus cycle is a write cycle. Write Byte Enable Upper Byte/Lower Byte Enable(In case of SRAM) nOE (Output Enable) indicates that the current bus cycle is a read cycle. nXBREQ (Bus Hold Request) allows another bus master to request control of the local bus. BACK active indicates that bus control has been granted. nXBACK (Bus Hold Acknowledge) indicates that the S3C2400 has surrendered control of the local bus to another bus master. nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the current bus cycle cannot be completed.
nWE nWBE[3:0] nBE[3:0] nOE nXBREQ nXBACK nWAIT
O O O O I O I
DRAM/SDRAM/SRAM nRAS[1:0] nCAS[3:0] nSRAS nSCAS nSCS[1:0] DQM[3:0] SCLK SCKE nBE[3:0] O O O O O O O O O Row Address Strobe Column Address strobe SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Chip Select SDRAM Data Mask SDRAM Clock SDRAM Clock Enable 16-bit SRAM Byte Enable
1-21
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
Table 1-3. S3C2400 Signal Descriptions (Continued) Signal I/O Description
LCD CONTROL UNIT VD[15:0] VCLK VFRAME VLINE VM VSYNC HSYNC VDEN LEND O O O O O O O O O STN/TFT: LCD Data Bus STN/TFT: LCD clock signal STN: LCD Frame signal STN: LCD line signal STN: VM alternates the polarity of the row and column voltage TFT: Vertical synchronous signal TFT: Horizontal synchronous signal TFT: Data enable signal TFT: Line End signal
INTERRUPT CONTROL UNIT EINT[7:0] DMA nXDREQ[1:0] nXDACK[1:0] UART RxD[1:0] TxD[1:0] nCTS[1:0] nRTS[1:0] IIC-BUS IICSDA IICSCL IIS-BUS I2SLRCK I2SSDO I2SSDI I2SSCLK CDCLK IO O I IO O IIS-bus channel select clock IIS-bus serial data output IIS-bus serial data input IIS-bus serial clock CODEC system clock IO IO IIC-bus data IIC-bus clock I O I O UART receives data input UART transmits data output UART clear to send input signal UART request to send output signal I O External DMA request External DMA acknowledge I External Interrupt request
1-22
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
Table 1-3. S3C2400 Signal Descriptions (Continued) Signal ADC AIN[7:0] Avref USB HOST DN[1:0] DP[1:0] USB DEVICE PDN0 PDP0 SPI SPIMISO SPIMOSI SPICLK nSS IO IO IO IO SPIMISO is the master data input line, when SPI is configured as a master. When SPI is configured as a slave, this pin reverse its role. SPIMOSI is the master data output line, when SPI is configured as a master. When SPI is configured as a slave, this pin reverse its role. SPI clock SPI chip select When SPI is configured as a master and ENMUL is set, nSS is a slave select. When SPI is configured as a slave, nSS is also a slave select. IO IO DATA - for USB peripheral DATA + for USB peripheral IO IO DATA - from USB host DATA + from USB host AI AI ADC input[7:0] ADC Vref I/O Description
MMC MMCDAT MMCCMD MMCCLK GENERAL PORT GPn[89:0] TIMMER/PWM TOUT[3:0] TCLK[1:0] O I Timer output[3:0] External clock input IO General input/output ports (some ports are output mode only) IO IO O MMC receive/transmit data MMC receive/transmit command MMC clock
1-23
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
Table 1-3. S3C2400 Signal Descriptions (Continued) Signal JTAG TEST LOGIC nTRST I nTRST(TAP Controller Reset) resets the TAP controller at start. If debugger is used, A 10K pull-up resistor has to be connected. If debugger(black ICE) is not used, nTRST pin must be at L or low active pulse. TMS (TAP Controller Mode Select) controls the sequence of the TAP controller's states. A 10K pull-up resistor has to be connected to TMS pin. TCK (TAP Controller Clock) provides the clock input for the JTAG logic. A 10K pull-up resistor must be connected to TCK pin. TDI (TAP Controller Data Input) is the serial input for test instructions and data. A 10K pull-up resistor must be connected to TDI pin. TDO (TAP Controller Data Output) is the serial output for test instructions and data. I/O Description
TMS TCK TDI TDO
I I I O
RESET & CLOCK & POWER nRESET ST nRESET suspends any operation in progress and places S3C2400 into a known reset state. For a reset, nRESET must be held to L level for at least 4 FCLK after the processor power has been stabilized. OM[3:2] determines how the clock is made. OM[3:2] = 00b, Crystal is used for MPLL CLK source and UPLL CLK source. OM[3:2] = 01b, Crystal is used for MPLL CLK source and EXTCLK is used for UPLL CLK source. OM[3:2] = 10b, EXTCLK is used for MPLL CLK source and Crystal is used for UPLL CLK source. OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source. EXTCLK I External clock source. When OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source. When OM[3:2] = 10b, EXTCLK is used for MPLL CLK source only. When OM[3:2] = 01b, EXTCLK is used for UPLL CLK source only. If it isn't used, it has to be H (3.3V). Crystal Input for internal osc circuit. When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source. When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only. When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only. If it isn't used, XTIpll has to be H (3.3V). Crystal Output for internal osc circuit. When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source. When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only. When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only. If it isn't used, it has to be a floating pin.
OM[3:2]
I
XTIpll
AI
XTOpll
AO
NOTES: 1. I/O means input/output. 2. AI/AO means analog input/output. 3. ST means schmitt-trigger. 4. P means power.
1-24
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
Table 1-3. S3C2400 Signal Descriptions (Continued) Signal I/O Description
RESET & CLOCK & POWER (continued) MPLLCAP UPLLCAP XTIrtc XTOrtc CLKOUT POWER VDDi VSSi VDDi_MPLL VSSi_MPLL VDDIO VSSIO RTCVDD VDDi_UPLL VSSi_UPLL VDDA_ADC VSSA_ADC P P P P P P P P P P P S3C2400 core logic VDD(1.8V) for CPU. S3C2400 core logic VSS S3C2400 MPLL analog and digital VDD (1.8 V). S3C2400 MPLL analog and digital VSS. S3C2400 I/O port VDD(3.3V) S3C2400 I/O port VSS RTC VDD (1.8 V, Not support 3.3V) (This pin must be connected to power properly if RTC isn't used) S3C2400 UPLL analog and digital VDD (1.8V) S3C2400 UPLL analog and digital VSS S3C2400 ADC VDD(3.3V) S3C2400 ADC VSS AI AI AI AO O Loop filter capacitor for main clock. Loop filter capacitor for USB clock. 32 KHz crystal input for RTC. 32 KHz crystal output for RTC. Clock output signal. The CLKSEL of MISCCR register configures the clock output mode among the MPLL CLK, UPLL CLK, FCLK, HCLK, PCLK.
1-25
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
S3C2400 SPECIAL REGISTERS Table 1-4. S3C2400 Special Registers Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function
MEMORY CONTROLLER BWSCON BANKCON0 BANKCON1 BANKCON2 BANKCON3 BANKCON4 BANKCON5 BANKCON6 BANKCON7 REFRESH BANKSIZE MRSRB6 MRSRB7 0x14000000 0x14000004 0x14000008 0x1400000c 0x14000010 0x14000014 0x14000018 0x1400001c 0x14000020 0x14000024 0x14000028 0x1400002c 0x14000030 W R/W Bus Width & Wait Status Control Boot ROM Control BANK1 Control BANK2 Control BANK3 Control BANK4 Control BANK5 Control BANK6 Control BANK7 Control DRAM/SDRAM Refresh Control Flexible Bank Size Mode register set for SDRAM Mode register set for SDRAM
1-26
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
Table 1-4. S3C2400 Special Registers (Continued) Register Name USB HOST CONTROLLER HcRevision HcControl HcCommonStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCuttentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcRmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2 INTERRUPT CONTROLLER SRCPND INTMOD INTMSK PRIORITY INTPND INTOFFSET 0x14400000 0x14400004 0x14400008 0x1440000c 0x14400010 0x14400014 W R/W W R/W W R/W R Interrupt Request Status Interrupt Mode Control Interrupt Mask Control IRQ Priority Control Interrupt Request Status Interrupt request source 0x14200000 0x14200004 0x14200008 0x1420000c 0x14200010 0x14200014 0x14200018 0x1420001c 0x14200020 0x14200024 0x14200028 0x1420002c 0x14200030 0x14200034 0x14200038 0x1420003c 0x14200040 0x14200044 0x14200048 0x1420004c 0x14200050 0x14200054 0x14200058 Root Hub Group Frame Counter Group Memory Pointer Group
Address (B. Endian)
Address (L. Endian)
Acc. Unit
Read/ Write
Function
W
Control and Status Group
1-27
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name DMA DISRC0 DIDST0 DCON0 DSTAT0 DCSRC0 DCDST0 DMASKTRIG0 DISRC1 DIDST1 DCON1 DSTAT1 DCSRC1 DCDST1 DMASKTRIG1 DISRC2 DIDST2 DCON2 DSTAT2 DCSRC2 DCDST2 DMASKTRIG2 DISRC3 DIDST3 DCON3 DSTAT3 DCSRC3 DCDST3 DMASKTRIG3 0x14600000 0x14600004 0x14600008 0x1460000c 0x14600010 0x14600014 0x14600018 0x14600020 0x14600024 0x14600028 0x1460002c 0x14600030 0x14600034 0x14600038 0x14600040 0x14600044 0x14600048 0x1460004c 0x14600050 0x14600054 0x14600058 0x14600060 0x14600064 0x14600068 0x1460006c 0x14600060 0x14600064 0x14600068 R/W R

Address (B. Endian)
Address (L. Endian)
Acc. Unit
Read/ Write
Function
W
R/W
DMA 0 Initial Source DMA 0 Initial Destination DMA 0 Control
R
DMA 0 Count DMA 0 Current Source Address DMA 0 Current Destination Address
R/W W R/W
DMA 0 Mask Trigger DMA 1 Initial Source DMA 1 Initial Destination DMA 1 Control
R
DMA 1 Count DMA 1 Current Source Address DMA 1 Current Destination Address
R/W W R/W
DMA 1 Mask Trigger DMA 2 Initial Source DMA 2 Initial Destination DMA 2 Control
R
DMA 2 Count DMA 2 Current Source Address DMA 2 Current Destination Address
R/W W R/W
DMA 2 Mask Trigger DMA 3 Initial Source DMA 3 Initial Destination DMA 3 Control DMA 3 Count DMA 3 Current Source Address DMA 3 Current Destination Address DMA 3 Mask Trigger
1-28
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
Table 1-4. S3C2400 Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function
CLOCK & POWER MANAGEMENT LOCKTIME MPLLCON UPLLCON CLKCON CLKSLOW CLKDIVN LCD CONTROLLER LCDCON1 LCDCON2 LCDCON3 LCDCON4 LCDCON5 LCDSADDR1 LCDSADDR2 LCDSADDR3 REDLUT GREENLUT BLUELUT DP1_2 DP4_7 DP3_5 DP2_3 DP5_7 DP3_4 DP4_5 DP6_7 DITHMODE TPAL 0x14a00000 0x14a00004 0x14a00008 0x14a0000c 0x14a00010 0x14a00014 0x14a00018 0x14a0001c 0x14a00020 0x14a00024 0x14a00028 0x14a0002c 0x14a00030 0x14a00034 0x14a00038 0x14a0003c 0x14a00040 0x14a00044 0x14a00048 0x14a0004c 0x14a00050 W R/W LCD Control 1 LCD Control 2 LCD Control 3 LCD Control 4 LCD Control 5 STN/TFT: Frame Buffer Start Address1 STN/TFT: Frame Buffer Start Address2 STN/TFT: Virtual Screen Address Set STN: Red Lookup Table STN: Green Lookup Table STN: Blue Lookup Table STN: Dithering Pattern Duty 1/2 STN: Dithering Pattern Duty 4/7 STN: Dithering Pattern Duty 3/5 STN: Dithering Pattern Duty 2/3 STN: Dithering Pattern Duty 5/7 STN: Dithering Pattern Duty 3/4 STN: Dithering Pattern Duty 4/5 STN: Dithering Pattern Duty 6/7 STN: Dithering Mode TFT: Temporary Palette 0x14800000 0x14800004 0x14800008 0x1480000c 0x14800010 0x14800014 W R/W PLL Lock Time Counter MPLL Control UPLL Control Clock Generator Control Slow Clock Control Clock divider Control
1-29
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name UART ULCON0 UCON0 UFCON0 UMCON0 UTRSTAT0 UERSTAT0 UFSTAT0 UMSTAT0 UTXH0 URXH0 UBRDIV0 ULCON1 UCON1 UFCON1 UMCON1 UTRSTAT1 UERSTAT1 UFSTAT1 UMSTAT1 UTXH1 URXH1 UBRDIV1 0x15000000 0x15000004 0x15000008 0x1500000c 0x15000010 0x15000014 0x15000018 0x1500001c 0x15000023 0x15000027 0x15000028 0x15004000 0x15004004 0x15004008 0x1500400c 0x15004010 0x15004014 0x15004018 0x1500401c 0x15004023 0x15004027 0x15004028 0x15004020 0x15004024

Address (B. Endian)
Address (L. Endian)
Acc. Unit
Read/ Write
Function
W
R/W
UART 0 Line Control UART 0 Control UART 0 FIFO Control UART 0 Modem Control
R
UART 0 Tx/Rx Status UART 0 Rx Error Status UART 0 FIFO Status UART 0 Modem Status
0x15000020 0x15000024

B
W R
UART 0 Transmission Hold UART 0 Receive Buffer UART 0 Baud Rate Divisor UART 1 Line Control UART 1 Control UART 1 FIFO Control UART 1 Modem Control
W W
R/W R/W
R
UART 1 Tx/Rx Status UART 1 Rx Error Status UART 1 FIFO Status UART 1 Modem Status
B
W R
UART 1 Transmission Hold UART 1 Receive Buffer UART 1 Baud Rate Divisor
W
R/W
1-30
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
Table 1-4. S3C2400 Special Registers (Continued) Register Name PWM TIMER TCFG0 TCFG1 TCON TCNTB0 TCMPB0 TCNTO0 TCNTB1 TCMPB1 TCNTO1 TCNTB2 TCMPB2 TCNTO2 TCNTB3 TCMPB3 TCNTO3 TCNTB4 TCNTO4 0x15100000 0x15100004 0x15100008 0x1510000c 0x15100010 0x15100014 0x15100018 0x1510001c 0x15100020 0x15100024 0x15100028 0x1510002c 0x15100030 0x15100034 0x15100038 0x1510003c 0x15100040 R R/W R R R/W R R/W R R/W
Address (B. Endian)
Address (L. Endian)
Acc. Unit
Read/ Write
Function
W
R/W
Timer Configuration Timer Configuration Timer Control Timer Count Buffer 0 Timer Compare Buffer 0 Timer Count Observation 0 Timer Count Buffer 1 Timer Compare Buffer 1 Timer Count Observation 1 Timer Count Buffer 2 Timer Compare Buffer 2 Timer Count Observation 2 Timer Count Buffer 3 Timer Compare Buffer 3 Timer Count Observation 3 Timer Count Buffer 4 Timer Count Observation 4
1-31
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name USB DEVICE FUNC_ADDR_REG PWR_REG INT_REG INT_MASK_REG FRAME_NUM_REG RESUME_CON_REG EP0_CSR EP0_MAXP EP0_OUT_CNT EP0_FIFO EP1_IN_CSR EP1_IN_MAXP EP1_FIFO EP2_IN_CSR EP2_IN_MAXP EP2_FIFO EP3_OUT_CSR EP3_OUT_MAXP EP3_OUT_CNT EP3_FIFO EP4_OUT_CSR EP4_OUT_MAXP EP4_OUT_CNT EP4_FIFO DMA_CON DMA_UNIT DMA_FIFO DMA_TX TEST_MODE IN_CON_REG 0x15200140 0x15200144 0x15200148 0x1520014c 0x15200150 0x15200154 0x15200160 0x15200164 0x15200168 0x1520016c 0x15200180 0x15200184 0x15200188 0x15200190 0x15200194 0x15200198 0x152001a0 0x152001a4 0x152001a8 0x152001ac 0x152001b0 0x152001b4 0x152001b8 0x152001bc 0x152001c0 0x152001c4 0x152001c8 0x152001cc 0x152001f4 0x152001f8 W R/W R R/W R W R/W W R/W R R/W R R/W
Address (B. Endian)
Address (L. Endian)
Acc. Unit
Read/W rite
Function
W
R/W
Function Address Power Management Interrupt Pending and Clear Interrupt Mask Frame Number Resume Signal Control Clock Generator Control End Point0 MAX Packet End Point0 Out Write Count End Point0 FIFO Read/Write End Point1 in Control Status End Point1 in MAX Packet End Point2 FIFO Write End Point2 in Control Status End Point2 in MAX Packet End Point2 FIFO Write End Point3 Out Control Status End Point3 Out MAX Packet End Point3 Out Write Count End Point3 FIFO Read End Point4 Out Control Status End Point4 Out MAX Packet End Point4 Out Write Count End Point4 FIFO Read DMA Interface Control DMA Transfer Unit Counter DMA Transfer FIFO Counter DMA Total Transfer Counter Test Mode Control In Packet Number Control
1-32
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
Table 1-4. S3C2400 Special Registers (Continued) Register Name WATCHDOG TIMER WTCON WTDAT WTCNT IIC IICCON IICSTAT IICADD IICDS IIS IISCON IISMOD IISPSR IISFIFCON IISFIF 0x15508000,02 0x15508004,06 0x15508008,0a 0x1550800c,0e 0x15508012 0x15508000 0x15508004 0x15508008 0x1550800c 0x15508010 HW,W HW,W HW,W HW,W HW R/W IIS Control IIS Mode IIS Prescaler IIS FIFO Control IIS FIFO Entry 0x15400000 0x15400004 0x15400008 0x1540000c
Address (B. Endian)
Address (L. Endian)
Acc. Unit
Read/ Write
Function
0x15300000 0x15300004 0x15300008
W
R/W
Watch-Dog Timer Mode Watch-Dog Timer Data Watch-Dog Timer Count
W
R/W
IIC Control IIC Status IIC Address IIC Data Shift
1-33
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name I/O PORT PACON PADAT PBCON PBDAT PBUP PCCON PCDAT PCUP PDCON PDDAT PDUP PECON PEDAT PEUP PFCON PFDAT PFUP PGCON PGDAT PGUP OPENCR MISCCR EXTINT 0x15600000 0x15600004 0x15600008 0x1560000c 0x15600010 0x15600014 0x15600018 0x1560001c 0x15600020 0x15600024 0x15600028 0x1560002c 0x15600030 0x15600034 0x15600038 0x1560003c 0x15600040 0x15600044 0x15600048 0x1560004c 0x15600050 0x15600054 0x15600058
Address (B. Endian)
Address (L. Endian)
Acc. Unit
Read/ Write
Function
W
R/W
Port A Control Port A Data Port B Control Port B Data Pull-up Control B Port C Control Port C Data Pull-up Control C Port D Control Port D Data Pull-up Control D Port E Control Port E Data Pull-up Control E Port F Control Port F Data Pull-up Control F Port G Control Port G Data Pull-up Control G Open Drain Enable Miscellaneous Control External Interrupt Control
1-34
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
Table 1-4. S3C2400 Special Registers (Continued) Register Name RTC RTCCON TICINT RTCALM ALMSEC ALMMIN ALMHOUR ALMDAY ALMMON ALMYEAR RTCRST BCDSEC BCDMIN BCDHOUR BCDDAY BCDDATE BCDMON BCDYEAR A/D CONVERTER ADCCON ADCDAT SPI SPCON SPSTA SPPIN SPPRE SPTDAT SPRDAT 0x15900000 0x15900004 0x15900008 0x1590000c 0x15900010 0x15900014 R
Address (B. Endian)
Address (L. Endian)
Acc. Unit
Read/ Write
Function
0x15700043 0x15700047 0x15700053 0x15700057 0x1570005b 0x1570005f 0x15700063 0x15700067 0x1570006b 0x1570006f 0x15700073 0x15700077 0x1570007b 0x1570007f 0x15700083 0x15700087 0x1570008b
0x15700040 0x15700044 0x15700050 0x15700054 0x15700058 0x1570005c 0x15700060 0x15700064 0x15700068 0x1570006c 0x15700070 0x15700074 0x15700078 0x1570007c 0x15700080 0x15700084 0x15700088
B
R/W
RTC Control Tick time count RTC Alarm Control Alarm Second Alarm Minute Alarm Hour Alarm Day Alarm Month Alarm Year RTC Round Reset BCD Second BCD Minute BCD Hour BCD Day BCD Date BCD Month BCD Year
0x15800000 0x15800004
W
R/W R
ADC Control ADC Data
W
R/W R R/W
SPI Control SPI Status SPI Pin Control SPI Baud Rate Prescaler SPI Tx Data SPI Rx Data
1-35
PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name MMC INTERFACE MMCON MMCRR MMFCON MMSTA MMFSTA MMPRE MMLEN MMCR7 MMRSP0 MMRSP1 MMRSP2 MMRSP3 MMCMD0 MMCMD1 MMCR16 MMDAT 0x15a00000,02,03 0x15a00004,06,07 0x15a00008,0a,0b 0x15a0000c,0e,0f 0x15a00010,12 0x15a00014,16,17 0x15a00018,1a 0x15a0001c,0e,0f 0x15a00020 0x15a00024 0x15a00028 0x15a0002c 0x15a00030,32,33 0x15a00034 0x15a00038,3a 0x15a0003c,3e,3f 0x15a00030
Address (B. Endian)
Address (L. Endian)
Acc. Unit
Read/ Write
Function
0x15a00000 0x15a00004 0x15a00008 0x15a0000c 0x15a00010 0x15a00014 0x15a00018 0x15a0001c
B, HW, W
R/W
MMC Control MMC Command MMC FIFO Control
R HW, W B, HW, W HW, W B, HW, W W R R/W
MMC Status MMC FIFO Status MMC Baud Rate Prescaler MMC Block Length Response CRC7 MMC Response Status 0 MMC Response Status 1 MMC Response Status 2 MMC Response Status 3
B, HW, W W HW, W B, HW, W
R/W
MMC Command 0 MMC Command 1
0x15a00038 0x15a0003c
R R/W
Data Read CRC16 Buffer MMC Data
1-36
S3C2400 RISC MICROPROCESSOR
PRODUCT OVERVIEW
IMPORTANT NOTES ABOUT S3C2400 SPECIAL REGISTERS 1. 2. 3. 4. 5. In the little endian mode, L. endian address must be used. In the big endian mode, B. endian address must be used. The special registers have to be accessed by the recommended access unit. All registers except ADC registers, RTC registers and UART registers must be read/written in word unit (32bit) at little/big endian. It is very important that the ADC registers, RTC registers and UART registers be read/written by the specified access unit and the specified address. Moreover, one must carefully consider which endian mode is used. W: 32-bit register, which must be accessed by LDR/STR or int type pointer(int *). HW: 16-bit register, which must be accessed by LDRH/STRH or short int type pointer(short int *). B: 8-bit register, which must be accessed by LDRB/STRB or char type pointer(char int *).
1-37
S3C2400X01 RISC MICROPROCESSOR
PROGRAMMER'S MODEL
2
OVERVIEW
* *
PROGRAMMER'S MODEL
S3C2400X01 has been developed using the advanced ARM920T core, which has been designed by Advanced RISC Machines, Ltd. PROCESSOR OPERATING STATES From the programmer's point of view, the ARM920T can be in one of two states: ARM state which executes 32-bit, word-aligned ARM instructions. THUMB state which can execute 16-bit, halfword-aligned THUMB instructions. In this state, the PC uses bit 1 to select between alternate halfwords. NOTE Transition between these two states does not affect the processor mode or the contents of the registers. SWITCHING STATE Entering THUMB State Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0) set in the operand register. Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT, SWI etc.), if the exception was entered with the processor in THUMB state. Entering ARM State Entry into ARM state happens: * * On execution of the BX instruction with the state bit clear in the operand register. On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.). In this case, the PC is placed in the exception mode's link register, and execution commences at the exception's vector address.
MEMORY FORMATS ARM920T views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. ARM920T can treat words in memory as being stored either in BigEndian or Little-Endian format.
2-1
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
BIG-ENDIAN FORMAT In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24.
Higher Address 31 8 4 0 Lower Address 24 23 9 5 1 16 15 10 6 2 8 7 11 7 3 0
Word Address 8 4 0
Most significant byte is at lowest address. Word is addressed by byte address of most significant byte.
Figure 2-1. Big-Endian Addresses of Bytes within Words LITTLE-ENDIAN FORMAT In Little-Endian format, the lowest numbered byte in a word is considered the word's least significant byte, and the highest numbered byte the most significant. Byte 0 of the memory system is therefore connected to data lines 7 through 0.
Higher Address 31 11 7 3 Lower Address 24 23 10 6 2 16 15 9 5 1 8 7 8 4 0 0
Word Address 8 4 0
Least significant byte is at lowest address. Word is addressed by byte address of least significant byte.
Figure 2-2. Little-Endian Addresses of Bytes whthin Words INSTRUCTION LENGTH Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). Data Types ARM920T supports byte (8-bit), halfword (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half words to two-byte boundaries.
2-2
S3C2400X01 RISC MICROPROCESSOR
PROGRAMMER'S MODEL
OPERATING MODES ARM920T supports seven modes of operation:
* * * * * * *
User (usr): The normal ARM program execution state FIQ (fiq): Designed to support a data transfer or channel process IRQ (irq): Used for general-purpose interrupt handling Supervisor (svc): Protected mode for the operating system Abort mode (abt): Entered after a data or instruction prefetch abort System (sys): A privileged user mode for the operating system Undefined (und): Entered when an undefined instruction is executed
Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs will execute in User mode. The non-user modes' known as privileged modesare entered in order to service interrupts or exceptions, or to access protected resources. REGISTERS ARM920T has a total of 37 registers - 31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. The processor state and operating mode dictate which registers are available to the programmer. The ARM State Register Set In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (nonUser) modes, mode-specific banked registers are switched in. Figure 2-3 shows which registers are available in each mode: the banked registers are marked with a shaded triangle. The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these except R15 are generalpurpose, and may be used to hold either data or address values. In addition to these, there is a seventeenth register used to store status information. Register 14 is used as the subroutine link register. This receives a copy of R15 when a Branch and Link (BL) instruction is executed. At all other times it may be treated as a generalpurpose register. The corresponding banked registers R14_svc, R14_irq, R14_fiq, R14_abt and R14_und are similarly used to hold the return values of R15 when interrupts and exceptions arise, or when Branch and Link instructions are executed within interrupt or exception routines. holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are zero and bits [31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain the PC. is the CPSR (Current Program Status Register). This contains condition code flags and the current mode bits.
Register 15 Register 16
FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state, many FIQ handlers do not need to save any registers. User, IRQ, Supervisor, Abort and Undefined each have two banked registers mapped to R13 and R14, allowing each of these modes to have a private stack pointer and link registers.
2-3
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
ARM State General Registers and Program Counter
System & User R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) FIQ R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R15 (PC) Supervisor R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_svc R14_svc R15 (PC) Abort R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_abt R14_abt R15 (PC) IRQ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_irq R14_irq R15 (PC) Undefined R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_und R14_und R15 (PC)
ARM State Program Status Registers
CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und
= banked register
Figure 2-3. Register Organization in ARM State
2-4
S3C2400X01 RISC MICROPROCESSOR
PROGRAMMER'S MODEL
The THUMB State Register Set The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each privileged mode. This is shown in Figure 2-4.
THUMB State General Registers and Program Counter
System & User R0 R1 R2 R3 R4 R5 R6 R7 SP LR PC FIQ R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq LR_fiq PC Supervisor R0 R1 R2 R3 R4 R5 R6 R7 SP_svc LR_svc PC Abort R0 R1 R2 R3 R4 R5 R6 R7 SP_abt LR_abt PC IRQ R0 R1 R2 R3 R4 R5 R6 R7 SP_und LR_und PC Undefined R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq LR_fiq PC
THUMB State Program Status Registers
CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und
= banked register
Figure 2-4. Register Organization in THUMB state
2-5
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
The relationship between ARM and THUMB state registers The THUMB state registers relate to the ARM state registers in the following way:
* * * * *
THUMB state R0-R7 and ARM state R0-R7 are identical THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical THUMB state SP maps onto ARM state R13 THUMB state LR maps onto ARM state R14 The THUMB state Program Counter maps onto the ARM state Program Counter (R15)
This relationship is shown in Figure 2-5.
THUMB state R0 R1 R2 R3 R4 R5 R6 R7
ARM state R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 Stack Pointer (R13) Link register (R14) Program Counter (R15) CPSR SPSR
Stack Pointer (SP) Link register (LR) Program Counter (PC) CPSR SPSR
Figure 2-5. Mapping of THUMB State Registers onto ARM State Registers
2-6
Hi-registers
Lo-registers
S3C2400X01 RISC MICROPROCESSOR
PROGRAMMER'S MODEL
Accessing Hi-Registers in THUMB State In THUMB state, registers R8-R15 (the Hi registers) are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage. A value may be transferred from a register in the range R0-R7 (a Lo register) to a Hi register, and from a Hi register to a Lo register, using special variants of the MOV instruction. Hi register values can also be compared against or added to Lo register values with the CMP and ADD instructions. For more information, refer to Figure 3-34. THE PROGRAM STATUS REGISTERS The ARM920T contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSRs) for use by exception handlers. These register's functions are:
* * *
Hold information about the most recently performed ALU operation Control the enabling and disabling of interrupts Set the processor operating mode
The arrangement of bits is shown in Figure 2-6.
Condition Code Flags 31 N 30 Z 29 C 28 V 27 26
(Reserved) 25 24 23 ~ ~ I ~ ~ Overflow Carry/Borrow/Extend Zero Negative/Less Than F T 8 7 6 5
Control Bits 4 M4 3 M3 2 M2 1 M1 0 M0
Mode bits State bit FIQ disable IRQ disable
Figure 2-6. Program Status Register Format
2-7
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
The Condition Code Flags The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed. In ARM state, all instructions may be executed conditionally: see Table 3-2 for details. In THUMB state, only the Branch instruction is capable of conditional execution: see Figure 3-46 for details. The Control Bits The bottom 8 bits of a PSR (incorporating I, F, T and M[4:0]) are known collectively as the control bits. These will be changed when an exception arises. If the processor is operating in a privileged mode, they can also be manipulated by software. The T bit This reflects the operating state. When this bit is set, the processor is executing in THUMB state, otherwise it is executing in ARM state. This is reflected on the TBIT external signal. Note that the software must never change the state of the TBIT in the CPSR. If this happens, the processor will enter an unpredictable state. Interrupt disable bits The mode bits The I and F bits are the interrupt disable bits. When set, these disable the IRQ and FIQ interrupts respectively. The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These determine the processor's operating mode, as shown in Table 2-1. Not all combinations of the mode bits define a valid processor mode. Only those explicitly described shall be used. The user should be aware that if any illegal value is programmed into the mode bits, M[4:0], then the processor will enter an unrecoverable state. If this occurs, reset should be applied. The remaining bits in the PSRs are reserved. When changing a PSR's flag or control bits, you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero.
Reserved bits
2-8
S3C2400X01 RISC MICROPROCESSOR
PROGRAMMER'S MODEL
Table 2-1. PSR Mode Bit Values M[4:0] 10000 User Mode Visible THUMB state registers R7..R0, LR, SP PC, CPSR R7..R0, LR_fiq, SP_fiq PC, CPSR, SPSR_fiq R7..R0, LR_irq, SP_irq PC, CPSR, SPSR_irq R7..R0, LR_svc, SP_svc, PC, CPSR, SPSR_svc R7..R0, LR_abt, SP_abt, PC, CPSR, SPSR_abt R7..R0 LR_und, SP_und, PC, CPSR, SPSR_und R7..R0, LR, SP PC, CPSR Visible ARM state registers R14..R0, PC, CPSR R7..R0, R14_fiq..R8_fiq, PC, CPSR, SPSR_fiq R12..R0, R14_irq, R13_irq, PC, CPSR, SPSR_irq R12..R0, R14_svc, R13_svc, PC, CPSR, SPSR_svc R12..R0, R14_abt, R13_abt, PC, CPSR, SPSR_abt R12..R0, R14_und, R13_und, PC, CPSR R14..R0, PC, CPSR
10001
FIQ
10010
IRQ
10011
Supervisor
10111
Abort
11011
Undefined
11111
System
Reserved bits
The remaining bits in the PSR's are reserved. When changing a PSR's flag or control bits, you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero.
2-9
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished. It is possible for several exceptions to arise at the same time. If this happens, they are dealt with in a fixed order. See Exception Priorities on page 2-14. Action on Entering an Exception When handling an exception, the ARM920T: 1. Preserves the address of the next instruction in the appropriate Link Register. If the exception has been entered from ARM state, then the address of the next instruction is copied into the Link Register (that is, current PC + 4 or PC + 8 depending on the exception. See Table 2-2 on for details). If the exception has been entered from THUMB state, then the value written into the Link Register is the current PC offset by a value such that the program resumes from the correct place on return from the exception. This means that the exception handler need not determine which state the exception was entered from. For example, in the case of SWI, MOVS PC, R14_svc will always return to the next instruction regardless of whether the SWI was executed in ARM or THUMB state. Copies the CPSR into the appropriate SPSR Forces the CPSR mode bits to a value which depends on the exception Forces the PC to fetch the next instruction from the relevant exception vector
2. 3. 4.
It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions. If the processor is in THUMB state when an exception occurs, it will automatically switch into ARM state when the PC is loaded with the exception vector address. Action on Leaving an Exception On completion, the exception handler: 1. 2. 3. Moves the Link Register, minus an offset where appropriate, to the PC. (The offset will vary depending on the type of exception.) Copies the SPSR back to the CPSR Clears the interrupt disable flags, if they were set on entry NOTE An explicit switch back to THUMB state is never needed, since restoring the CPSR from the SPSR automatically sets the T bit to the value it held immediately prior to the exception.
2-10
S3C2400X01 RISC MICROPROCESSOR
PROGRAMMER'S MODEL
Exception Entry/Exit Summary Table 2-2 summarises the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler. Table2-2. Exception Entry/Exit Return Instruction Previous State ARM R14_x BL SWI UDEF FIQ IRQ PABT DABT RESET MOV PC, R14 MOVS PC, R14_svc MOVS PC, R14_und SUBS PC, R14_fiq, #4 SUBS PC, R14_irq, #4 SUBS PC, R14_abt, #4 SUBS PC, R14_abt, #8 NA PC + 4 PC + 4 PC + 4 PC + 4 PC + 4 PC + 4 PC + 8 THUMB R14_x PC + 2 PC + 2 PC + 2 PC + 4 PC + 4 PC + 4 PC + 8 1 1 1 2 2 1 3 4 Notes
NOTES: 1. Where PC is the address of the BL/SWI/Undefined Instruction fetch which had the prefetch abort. 2. Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority. 3. Where PC is the address of the Load or Store instruction which generated the data abort. 4. The value saved in R14_svc upon reset is unpredictable.
FIQ The FIQ (Fast Interrupt Request) exception is designed to support a data transfer or channel process, and in ARM state has sufficient private registers to remove the need for register saving (thus minimising the overhead of context switching). FIQ is externally generated by taking the nFIQ input LOW. This input can except either synchronous or asynchronous transitions, depending on the state of the ISYNC input signal. When ISYNC is LOW, nFIQ and nIRQ are considered asynchronous, and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow. Irrespective of whether the exception was entered from ARM or Thumb state, a FIQ handler should leave the interrupt by executing SUBS PC,R14_fiq,#4
FIQ may be disabled by setting the CPSR's F flag (but note that this is not possible from User mode). If the F flag is clear, ARM920T checks for a LOW level on the output of the FIQ synchroniser at the end of each instruction.
2-11
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
IRQ The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting the I bit in the CPSR, though this can only be done from a privileged (non-User) mode. Irrespective of whether the exception was entered from ARM or Thumb state, an IRQ handler should return from the interrupt by executing SUBS Abort An abort indicates that the current memory access cannot be completed. It can be signalled by the external ABORT input. ARM920T checks for the abort exception during memory access cycles. There are two types of abort:
* *
PC,R14_irq,#4
Prefetch abort: occurs during an instruction prefetch. Data abort: occurs during a data access.
If a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until the instruction reaches the head of the pipeline. If the instruction is not executed - for example because a branch occurs while it is in the pipeline - the abort does not take place. If a data abort occurs, the action taken depends on the instruction type:
* * *
Single data transfer instructions (LDR, STR) write back modified base registers: the Abort handler must be aware of this. The swap instruction (SWP) is aborted as though it had not been executed. Block data transfer instructions (LDM, STM) complete. If write-back is set, the base is updated. If the instruction would have overwritten the base with data (ie it has the base in the transfer list), the overwriting is prevented. All register overwriting is prevented after an abort is indicated, which means in particular that R15 (always the last register to be transferred) is preserved in an aborted LDM instruction.
The abort mechanism allows the implementation of a demand paged virtual memory system. In such a system the processor is allowed to generate arbitrary addresses. When the data at an address is unavailable, the Memory Management Unit (MMU) signals an abort. The abort handler must then work out the cause of the abort, make the requested data available, and retry the aborted instruction. The application program needs no knowledge of the amount of memory available to it, nor is its state in any way affected by the abort. After fixing the reason for the abort, the handler should execute the following irrespective of the state (ARM or Thumb): SUBS SUBS PC,R14_abt,#4 PC,R14_abt,#8 ; for a prefetch abort, or ; for a data abort
This restores both the PC and the CPSR, and retries the aborted instruction.
2-12
S3C2400X01 RISC MICROPROCESSOR
PROGRAMMER'S MODEL
Software Interrupt The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb): MOV PC,R14_svc
This restores the PC and CPSR, and returns to the instruction following the SWI. NOTE nFIQ, nIRQ, ISYNC, LOCK, BIGEND, and ABORT pins exist only in the ARM920T CPU core. Undefined Instruction When ARM920T comes across an instruction which it cannot handle, it takes the undefined instruction trap. This mechanism may be used to extend either the THUMB or ARM instruction set by software emulation. After emulating the failed instruction, the trap handler should execute the following irrespective of the state (ARM or Thumb): MOVS PC,R14_und
This restores the CPSR and returns to the instruction following the undefined instruction. Exception Vectors The following table shows the exception vector addresses. Table 2-3. Exception Vectors Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C Reset Undefined instruction Software Interrupt Abort (prefetch) Abort (data) Reserved IRQ FIQ Exception Supervisor Undefined Supervisor Abort Abort Reserved IRQ FIQ Mode in Entry
2-13
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
Exception Priorites When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1. 2. 3. 4. 5. Reset Data abort FIQ IRQ Prefetch abort
Lowest priority: 6. Undefined Instruction, Software interrupt.
Not All Exceptions Can Occur at Once: Undefined Instruction and Software Interrupt are mutually exclusive, since they each correspond to particular (nonoverlapping) decodings of the current instruction. If a data abort occurs at the same time as a FIQ, and FIQs are enabled (ie the CPSR's F flag is clear), ARM920T enters the data abort handler and then immediately proceeds to the FIQ vector. A normal return from FIQ will cause the data abort handler to resume execution. Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection. The time for this exception entry should be added to worst-case FIQ latency calculations.
2-14
S3C2400X01 RISC MICROPROCESSOR
PROGRAMMER'S MODEL
INTERRUPT LATENCIES The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchroniser (Tsyncmax if asynchronous), plus the time for the longest instruction to complete (Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data abort entry (Texc), plus the time for FIQ entry (Tfiq). At the end of this time ARM920T will be executing the instruction at 0x1C. Tsyncmax is 3 processor cycles, Tldm is 20 cycles, Texc is 3 cycles, and Tfiq is 2 cycles. The total time is therefore 28 processor cycles. This is just over 1.4 microseconds in a system which uses a continuous 20 MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchroniser (Tsyncmin) plus Tfiq. This is 4 processor cycles. RESET When the nRESET signal goes LOW, ARM920T abandons the executing instruction and then continues to fetch instructions from incrementing word addresses. When nRESET goes HIGH again, ARM920T: 1. 2. 3. 4. Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The value of the saved PC and SPSR is not defined. Forces M[4:0] to 10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR's T bit. Forces the PC to fetch the next instruction from address 0x00. Execution resumes in ARM state.
2-15
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
NOTES
2-16
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
3
ARM INSTRUCTION SET
INSTRUCTION SET SUMMAY
This chapter describes the ARM instruction set in the ARM920T core.
FORMAT SUMMARY The ARM instruction set formats are shown below.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond 00I Opcode S Rn Rd RdHi Rn Rd Rn RdLo Rd Operand2 Rs Rn 1001 1001 Rm Rm Rm Rn Rm Offset Data/Processing/ PSR Transfer Multiply Multiply Long Single Data Swap Branch and Exchange Halfword Data Transfer: register offset Halfword Data Transfer: immendiate offset Single Data Transfer 1 Rn Offset Rn CRn CRn CRd CRd Rd CP# CP# CP# CP CP Offset 0 1 CRm CRm Register List Undefined Block Data Transfer Branch Coprocessor Data Transfer Coprocessor Data Operation Coprocessor Register Transfer Software Interrupt
0 00000AS 0 0 0 0 1UAS 00010B00
00001001
000100101111111111110001 0 0 0 PU0WL 0 0 0 PU1WL 0 1 I PU BWL 01I 1 0 0 PU BWL 101L 1 1 0 PU BWL 1110 1110 1111 CP Opc CP Opc L Rn Rn Rn Rd Rd Rd 00001SH1 Offset 1SH1 Offset
Ignored by processor
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 3-1. ARM Instruction Set Format
3-1
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
NOTES Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken, for instance a Multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their action may change in future ARM implementations.
INSTRUCTION SUMMARY Table 3-1. The ARM Instruction Set Mnemonic ADC ADD AND B BIC BL BX CDP CMN CMP EOR LDC LDM LDR MCR MLA MOV Add with carry Add AND Branch Bit Clear Branch with Link Branch and Exchange Coprocessor Data Processing Compare Negative Compare Exclusive OR Load coprocessor from memory Load multiple registers Load register from memory Move CPU register to coprocessor register Multiply Accumulate Move register or constant Instruction Action Rd: = Rn + Op2 + Carry Rd: = Rn + Op2 Rd: = Rn AND Op2 R15: = address Rd: = Rn AND NOT Op2 R14: = R15, R15: = address R15: = Rn, T bit: = Rn[0] (Coprocessor-specific) CPSR flags: = Rn + Op2 CPSR flags: = Rn - Op2 Rd: = (Rn AND NOT Op2) OR (Op2 AND NOT Rn) Coprocessor load Stack manipulation (Pop) Rd: = (address) cRn: = rRn {cRm} Rd: = (Rm x Rs) + Rn Rd: = Op2
3-2
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
Table 3-1. The ARM Instruction Set (Continued) Mnemonic MRC MRS MSR MUL MVN ORR RSB RSC SBC STC STM STR SUB SWI SWP TEQ TST Instruction Move from coprocessor register to CPU register Move PSR status/flags to register Move register to PSR status/flags Multiply Move negative register OR Reverse Subtract Reverse Subtract with Carry Subtract with Carry Store coprocessor register to memory Store Multiple Store register to memory Subtract Software Interrupt Swap register with memory Test bitwise equality Test bits Action Rn: = cRn {cRm} Rn: = PSR PSR: = Rm Rd: = Rm x Rs Rd: = 0 x FFFFFFFF EOR Op2 Rd: = Rn OR Op2 Rd: = Op2 - Rn Rd: = Op2 - Rn - 1 + Carry Rd: = Rn - Op2 - 1 + Carry address: = CRn Stack manipulation (Push)

: = Rd Rd: = Rn - Op2 OS call Rd: = [Rn], [Rn] := Rm CPSR flags: = Rn EOR Op2 CPSR flags: = Rn AND Op2
3-3
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
THE CONDITION FIELD
In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction's condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be executed. If the state of the C, N, Z and V flags fulfils the conditions encoded by the field, the instruction is executed, otherwise it is ignored. There are sixteen possible conditions, each represented by a two-character suffix that can be appended to the instruction's mnemonic. For example, a Branch (B in assembly language) becomes BEQ for "Branch if Equal", which means the Branch will only be taken if the Z flag is set. In practice, fifteen different conditions may be used: these are listed in Table 3-2. The sixteenth (1111) is reserved, and must not be used. In the absence of a suffix, the condition field of most instructions is set to "Always" (suffix AL). This means the instruction will always be executed regardless of the CPSR condition codes. Table 3-2. Condition Code Summary Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Suffix EQ NE CS CC MI PL VS VC HI LS GE LT GT LE AL Z set Z clear C set C clear N set N clear V set V clear C set and Z clear C clear or Z set N equals V N not equal to V Z clear AND (N equals V) Z set OR (N not equal to V) (ignored) Flags equal not equal unsigned higher or same unsigned lower negative positive or zero overflow no overflow unsigned higher unsigned lower or same greater or equal less than greater than less than or equal always Meaning
3-4
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
BRANCH AND EXCHANGE (BX)
This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. This instruction performs a branch by copying the contents of a general register, Rn, into the program counter, PC. The branch causes a pipeline flush and refill from the address specified by Rn. This instruction also permits the instruction set to be exchanged. When the instruction is executed, the value of Rn[0] determines whether the instruction stream will be decoded as ARM or THUMB instructions.
31 Cond
28 27
24 23
20 19
16 15
12 11
87
43 Rn
0
000100101111111111110001
[3:0] Operand Register
If bit0 of Rn = 1, subsequent instructions decoded as THUMB instructions If bit0 of Rn =0, subsequent instructions decoded as ARM instructions
[31:28] Condition Field
Figure 3-2. Branch and Exchange Instructions INSTRUCTION CYCLE TIMES The BX instruction takes 2S + 1N cycles to execute, where S and N are defined as sequential (S-cycle) and nonsequential (N-cycle), respectively.
ASSEMBLER SYNTAX BX - branch and exchange. BX {cond} Rn {cond} Rn
Two character condition mnemonic. See Table 3-2. is an expression evaluating to a valid register number.
USING R15 AS AN OPERAND If R15 is used as an operand, the behavior is undefined.
3-5
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
Examples ADR R0, Into_THUMB + 1 ; ; ; ; ; ; ; Generate branch target address and set bit 0 high - hence arrive in THUMB state. Branch and change to THUMB state. Assemble subsequent code as THUMB instructions
BX CODE16 Into_THUMB
* * *
R0
ADR R5, Back_to_ARM BX R5
* * *
; Generate branch target to word aligned address ; - hence bit 0 is low and so change back to ARM state. ; Branch and change back to ARM state.
ALIGN CODE32 Back_to_ARM
; Word align ; Assemble subsequent code as ARM instructions
3-6
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
BRANCH AND BRANCH WITH LINK (B, BL)
The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction encoding is shown in Figure 3-3, below.
31 Cond
28 27 101
25 24 23 L Offset
0
[24] Link bit
0 = Branch 1 = Branch with link
[31:28] Condition Field
Figure 3-3. Branch Instructions Branch instructions contain a signed 2's complement 24 bit offset. This is shifted left two bits, sign extended to 32 bits, and added to the PC. The instruction can therefore specify a branch of +/- 32Mbytes. The branch offset must take account of the prefetch operation, which causes the PC to be 2 words (8 bytes) ahead of the current instruction. Branches beyond +/- 32Mbytes must use an offset or absolute destination which has been previously loaded into a register. In this case the PC should be manually saved in R14 if a Branch with Link type operation is required.
THE LINK BIT Branch with Link (BL) writes the old PC into the link register (R14) of the current bank. The PC value written into R14 is adjusted to allow for the prefetch, and contains the address of the instruction following the branch and link instruction. Note that the CPSR is not saved with the PC and R14[1:0] are always cleared. To return from a routine called by Branch with Link use MOV PC,R14 if the link register is still valid or LDM Rn!,{..PC} if the link register has been saved onto a stack pointed to by Rn.
INSTRUCTION CYCLE TIMES Branch and Branch with Link instructions take 2S + 1N incremental cycles, where S and N are defined as sequential (S-cycle) and internal (I-cycle).
3-7
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
ASSEMBLER SYNTAX Items in {} are optional. Items in <> must be present. B{L}{cond} {L} {cond} Examples here BAL B CMP BEQ BL ADDS BLCC here there R1,#0 fred sub+ROM R1,#1 sub ; ; ; ; ; ; ; ; ; ; Assembles to 0xEAFFFFFE (note effect of PC offset). Always condition used as default. Compare R1 with zero and branch to fred if R1 was zero, otherwise continue. Continue to next instruction. Call subroutine at computed address. Add 1 to register 1, setting CPSR flags on the result then call subroutine if the C flag is clear, which will be the case unless R1 held 0xFFFFFFFF. Used to request the Branch with Link form of the instruction. If absent, R14 will not be affected by the instruction. A two-character mnemonic as shown in Table 3-2. If absent then AL (ALways) will be used. The destination. The assembler calculates the offset.
3-8
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
DATA PROCESSING
The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-4.
31 Cond
28 27 26 25 24 00 L
21 20 19 S Rn
16 15 Rd
12 11 Operand2
0
OpCode
[15:12] Destination register
0 = Branch 1 = Branch with link
[19:16] 1st operand register
0 = Branch 1 = Branch with link
[20] Set condition codes
0 = Do not after condition codes 1 = Set condition codes
[24:21] Operation codes
0000 = AND-Rd: = Op1 AND Op2 0001 = EOR-Rd: = Op1 EOR Op2 0010 = SUB-Rd: = Op1-Op2 0011 = RSB-Rd: = Op2-Op1 0100 = ADD-Rd: = Op1+Op2 0101 = ADC-Rd: = Op1+Op2+C 0110 = SBC-Rd: = OP1-Op2+C-1 0111 = RSC-Rd: = Op2-Op1+C-1 1000 = TST-set condition codes on Op1 AND Op2 1001 = TEO-set condition codes on OP1 EOR Op2 1010 = CMP-set condition codes on Op1-Op2 1011 = SMN-set condition codes on Op1+Op2 1100 = ORR-Rd: = Op1 OR Op2 1101 = MOV-Rd: =Op2 1110 = BIC-Rd: = Op1 AND NOT Op2 1111 = MVN-Rd: = NOT Op2
[25] Immediate operand
0 = Operand 2 is a register 1 = Operand 2 is an immediate value
[11:0] Operand 2 type selection
11 Shift [3:0] 2nd operand register 11 Rotate 87 Imm [11:8] Shift applied to Imm 0 34 Rm [11:4] Shift applied to Rm 0
[7:0] Unsigned 8 bit immediate value
[31:28] Condition field Figure 3-4. Data Processing Instructions
3-9
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. The first operand is always a register (Rn). The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction. The condition codes in the CPSR may be preserved or updated as a result of this instruction, according to the value of the S bit in the instruction. Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd. They are used only to perform tests and to set the condition codes on the result and always have the S bit set. The instructions and their effects are listed in Table 3-3.
3-10
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
CPSR FLAGS The data processing operations may be classified as logical or arithmetic. The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to produce the result. If the S bit is set (and Rd is not R15, see below) the V flag in the CPSR will be unaffected, the C flag will be set to the carry out from the barrel shifter (or preserved when the shift operation is LSL #0), the Z flag will be set if and only if the result is all zeros, and the N flag will be set to the logical value of bit 31 of the result. Table 3-3. ARM Data Processing Instructions Assembler Mnemonic AND EOR WUB RSB ADD ADC SBC RSC TST TEQ CMP CMN ORR MOV BIC MVN OP Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Operand1 AND operand2 Operand1 EOR operand2 Operand1 - operand2 Operand2 operand1 Operand1 + operand2 Operand1 + operand2 + carry Operand1 - operand2 + carry - 1 Operand2 - operand1 + carry - 1 As AND, but result is not written As EOR, but result is not written As SUB, but result is not written As ADD, but result is not written Operand1 OR operand2 Operand2 (operand1 is ignored) Operand1 AND NOT operand2 (Bit clear) NOT operand2 (operand1 is ignored) Action
The arithmetic operations (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN) treat each operand as a 32 bit integer (either unsigned or 2's complement signed, the two are equivalent). If the S bit is set (and Rd is not R15) the V flag in the CPSR will be set if an overflow occurs into bit 31 of the result; this may be ignored if the operands were considered unsigned, but warns of a possible error if the operands were 2's complement signed. The C flag will be set to the carry out of bit 31 of the ALU, the Z flag will be set if and only if the result was zero, and the N flag will be set to the value of bit 31 of the result (indicating a negative result if the operands are considered to be 2's complement signed).
3-11
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
SHIFTS When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the Shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). The amount by which the register should be shifted may be contained in an immediate field in the instruction, or in the bottom byte of another register (other than R15). The encoding for the different shift types is shown in Figure 3-5.
11
7654 0
11 RS
87654 0 1
[6:5] Shift type
00 = logical left 10 = arithmetic right 01 = logical right 11 = rotate right
[6:5] Shift type
00 = logical left 10 = arithmetic right 01 = logical right 11 = rotate right
[11:7] Shift amount
5 bit unsigned integer
[11:8] Shift register
Shift amount specified in bottom-byte of Rs
Figure 3-5. ARM Shift Operations Instruction specified shift amount When the shift amount is specified in the instruction, it is contained in a 5 bit field which may take any value from 0 to 31. A logical shift left (LSL) takes the contents of Rm and moves each bit by the specified amount to a more significant position. The least significant bits of the result are filled with zeros, and the high bits of Rm which do not map into the result are discarded, except that the least significant discarded bit becomes the shifter carry output which may be latched into the C bit of the CPSR when the ALU operation is in the logical class (see above). For example, the effect of LSL #5 is shown in Figure 3-6.
31
27 26 Contents of Rm
0
carry out
Value of Operand 2
00000
Figure 3-6. Logical Shift Left NOTES LSL #0 is a special case, where the shifter carry out is the old value of the CPSR C flag. The contents of Rm are used directly as the second operand. A logical shift right (LSR) is similar, but the contents of Rm are moved to less significant positions in the result. LSR #5 has the effect shown in Figure 3-7.
3-12
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
31 Contents of Rm
54
0
carry out
00000
Value of Operand 2
Figure 3-7. Logical Shift Right The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is the same as logical shift left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow LSR #32 to be specified. An arithmetic shift right (ASR) is similar to logical shift right, except that the high bits are filled with bit 31 of Rm instead of zeros. This preserves the sign in 2's complement notation. For example, ASR #5 is shown in Figure 3-8.
31 30 Contents of Rm
54
0
carry out
Value of Operand 2
Figure 3-8. Arithmetic Shift Right The form of the shift field which might be expected to give ASR #0 is used to encode ASR #32. Bit 31 of Rm is again used as the carry output, and each bit of operand 2 is also equal to bit 31 of Rm. The result is therefore all ones or all zeros, according to the value of bit 31 of Rm.
3-13
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
Rotate right (ROR) operations reuse the bits which "overshoot" in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. For example, ROR #5 is shown in Figure 3-9.
31 Contents of Rm
54
0
carry out
Value of Operand 2
Figure 3-9. Rotate Right The form of the shift field which might be expected to give ROR #0 is used to encode a special function of the barrel shifter, rotate right extended (RRX). This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3-10.
31 Contents of Rm
10
C in Value of Operand 2
carry out
Figure 3-10. Rotate Right Extended
3-14
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
Register Specified Shift Amount Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any general register other than R15. If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the CPSR C flag will be passed on as the shifter carry output. If the byte has a value between 1 and 31, the shifted result will exactly match that of an instruction specified shift with the same value and shift operation. If the value in the byte is 32 or more, the result will be a logical extension of the shift described above: 1. 2. 3. 4. 5. 6. 7. LSL by 32 has result zero, carry out equal to bit 0 of Rm. LSL by more than 32 has result zero, carry out zero. LSR by 32 has result zero, carry out equal to bit 31 of Rm. LSR by more than 32 has result zero, carry out zero. ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm. ROR by 32 has result equal to Rm, carry out equal to bit 31 of Rm. ROR by n where n is greater than 32 will give the same result and carry out as ROR by n-32; therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above. NOTES The zero in bit 7 of an instruction with a register controlled shift is compulsory; a one in this bit will cause the instruction to be a multiply or undefined instruction.
3-15
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value. This value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field. This enables many common constants to be generated, for example all powers of 2. WRITING TO R15 When Rd is a register other than R15, the condition code flags in the CPSR may be updated from the ALU flags as described above. When Rd is R15 and the S flag in the instruction is not set the result of the operation is placed in R15 and the CPSR is unaffected. When Rd is R15 and the S flag is set the result of the operation is placed in R15 and the SPSR corresponding to the current mode is moved to the CPSR. This allows state changes which atomically restore both PC and CPSR. This form of instruction should not be used in User mode. USING R15 AS AN OPERANDY If R15 (the PC) is used as an operand in a data processing instruction the register is used directly. The PC value will be the address of the instruction, plus 8 or 12 bytes due to instruction prefetching. If the shift amount is specified in the instruction, the PC will be 8 bytes ahead. If a register is used to specify the shift amount the PC will be 12 bytes ahead. TEQ, TST, CMP AND CMN OPCODES NOTES TEQ, TST, CMP and CMN do not write the result of their operation but do set flags in the CPSR. An assembler should always set the S flag for these instructions even if this is not specified in the mnemonic. The TEQP form of the TEQ instruction used in earlier ARM processors must not be used: the PSR transfer operations should be used instead. The action of TEQP in the ARM920T is to move SPSR_ to the CPSR if the processor is in a privileged mode and to do nothing if in User mode. INSTRUCTION CYCLE TIMES Data Processing instructions vary in the number of incremental cycles taken as follows: Table 3-4. Incremental Cycle Times Processing Type Normal data processing Data processing with register specified shift Data processing with PC written Data processing with register specified shift and PC written
NOTE:
Cycles 1S 1S + 1I 2S + 1N 2S + 1N +1I
S, N and I are as defined sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle) respectively.
3-16
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
ASSEMBLER SYNTAX
* * *
MOV,MVN (single operand instructions). {cond}{S} Rd, CMP,CMN,TEQ,TST (instructions which do not produce a result). {cond} Rn, AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC {cond}{S} Rd,Rn,
where: {cond} {S} Rm{,} or,<#expression> A two-character condition mnemonic. See Table 3-2. Set condition codes if S present (implied for CMP, CMN, TEQ, TST).
Rd, Rn and Rm Expressions evaluating to a register number. <#expression> s If this is used, the assembler will attempt to generate a shifted immediate 8-bit field to match the expression. If this is impossible, it will give an error. or #expression, or RRX (rotate right one bit with extend). ASL, LSL, LSR, ASR, ROR. (ASL is a synonym for LSL, they assemble to the same code.)
EXAMPLES ADDEQ TEQS R2,R4,R5 R4,#3 ; ; ; ; ; ; ; ; ; ; If the Z flag is set make R2:=R4+R5 Test R4 for equality with 3. (The S is in fact redundant as the assembler inserts it automatically.) Logical right shift R7 by the number in the bottom byte of R2, subtract result from R5, and put the answer into R4. Return from subroutine. Return from exception and restore CPSR from SPSR_mode.
SUB
R4,R5,R7,LSR R2
MOV MOVS
PC,R14 PC,R14
3-17
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
PSR TRANSFER (MRS, MSR)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented using the TEQ, TST, CMN and CMP instructions without the S flag set. The encoding is shown in Figure 3-11. These instructions allow access to the CPSR and SPSR registers. The MRS instruction allows the contents of the CPSR or SPSR_ to be moved to a general register. The MSR instruction allows the contents of a general register to be moved to the CPSR or SPSR_ register. The MSR instruction also allows an immediate value or register contents to be transferred to the condition code flags (N,Z,C and V) of CPSR or SPSR_ without affecting the control bits. In this case, the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR.
OPERAND RESTRICTIONS
* * * * *
In user mode, the control bits of the CPSR are protected from change, so only the condition code flags of the CPSR can be changed. In other (privileged) modes the entire CPSR can be changed. Note that the software must never change the state of the T bit in the CPSR. If this happens, the processor will enter an unpredictable state. The SPSR register which is accessed depends on the mode at the time of execution. For example, only SPSR_fiq is accessible when the processor is in FIQ mode. You must not specify R15 as the source or destination register. Also, do not attempt to access an SPSR in User mode, since no such register exists.
3-18
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
MRS (transfer PSR contents to a register)
31 Cond 28 27 00010 23 22 21 Ps 001111 16 15 Rd 12 11 000000000000 0
[15:12] Destination Register [22] Source PSR
0 = CPSR 1 = SPSR_
[31:28] Condition Field MSR (transfer register contents to PSR)
31 Cond 28 27 00010 23 22 21 Pd 101001111 12 11 00000000 43 Rm 0
[3:0] Source Register [22] Destination PSR
0 = CPSR 1 = SPSR_
[31:28] Condition Field MSR (transfer register contents or immediate value to PSR flag bits only)
31 Cond 28 27 26 25 24 23 22 21 00 I 10 Pd 101001111 12 11 Source operand 0
[22] Destination PSR
0 = CPSR 1 = SPSR_
[25] Immediate Operand
0 = Source operand is a register 1 = SPSR_
[11:0] Source Operand
11 00000000 43 Rm 0
[3:0] Source Register [11:4] Source operand is an immediate value 11 Rotate 87 Imm 0
[7:0] Unsigned 8 bit immediate value [11:8] Shift applied to Imm
[31:28] Condition Field Figure 3-11. PSR Transfer
3-19
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
RESERVED BITS Only twelve bits of the PSR are defined in ARM920T (N,Z,C,V,I,F, T & M[4:0]); the remaining bits are reserved for use in future versions of the processor. Refer to Figure 2-6 for a full description of the PSR bits. To ensure the maximum compatibility between ARM920T programs and future processors, the following rules should be observed: * * The reserved bits should be preserved when changing the value in a PSR. Programs should not rely on specific values from the reserved bits when checking the PSR status, since they may read as one or zero in future processors.
A read-modify-write strategy should therefore be used when altering the control bits of any PSR register; this involves transferring the appropriate PSR register to a general register using the MRS instruction, changing only the relevant bits and then transferring the modified value back to the PSR register using the MSR instruction.
EXAMPLES The following sequence performs a mode change: MRS BIC ORR MSR R0,CPSR R0,R0,#0x1F R0,R0,#new_mode CPSR,R0 ; ; ; ; Take a copy of the CPSR. Clear the mode bits. Select new mode Write back the modified CPSR.
When the aim is simply to change the condition code flags in a PSR, a value can be written directly to the flag bits without disturbing the control bits. The following instruction sets the N,Z,C and V flags: MSR CPSR_flg,#0xF0000000 ; Set all the flags regardless of their previous state ; (does not affect any control bits).
No attempt should be made to write an 8 bit immediate value into the whole PSR since such an operation cannot preserve the reserved bits.
INSTRUCTION CYCLE TIMES PSR transfers take 1S incremental cycles, where S is defined as Sequential (S-cycle).
3-20
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
ASSEMBLY SYNTAX
* * *
MRS - transfer PSR contents to a register MRS{cond} Rd, MSR - transfer register contents to PSR MSR{cond} ,Rm MSR - transfer register contents to PSR flag bits only MSR{cond} ,Rm
The most significant four bits of the register contents are written to the N,Z,C & V flags respectively.
*
MSR - transfer immediate value to PSR flag bits only MSR{cond} ,<#expression>
The expression should symbolise a 32 bit value of which the most significant four bits are written to the N,Z,C and V flags respectively. Key: {cond} Rd and Rm <#expression> Two-character condition mnemonic. See Table 3-2.. Expressions evaluating to a register number other than R15 CPSR, CPSR_all, SPSR or SPSR_all. (CPSR and CPSR_all are synonyms as are SPSR and SPSR_all) CPSR_flg or SPSR_flg Where this is used, the assembler will attempt to generate a shifted immediate 8-bit field to match the expression. If this is impossible, it will give an error.
EXAMPLES In User mode the instructions behave as follows: MSR MSR MSR MRS CPSR_all,Rm CPSR_flg,Rm CPSR_flg,#0xA0000000 Rd,CPSR ; ; ; ; CPSR[31:28] <- Rm[31:28] CPSR[31:28] <- Rm[31:28] CPSR[31:28] <- 0xA (set N,C; clear Z,V) Rd[31:0] <- CPSR[31:0]
In privileged modes the instructions behave as follows: MSR MSR MSR MSR MSR MSR MRS CPSR_all,Rm CPSR_flg,Rm CPSR_flg,#0x50000000 SPSR_all,Rm SPSR_flg,Rm SPSR_flg,#0xC0000000 Rd,SPSR ; ; ; ; ; ; ; CPSR[31:0] <- Rm[31:0] CPSR[31:28] <- Rm[31:28] CPSR[31:28] <- 0x5 (set Z,V; clear N,C) SPSR_[31:0]<- Rm[31:0] SPSR_[31:28] <- Rm[31:28] SPSR_[31:28] <- 0xC (set N,Z; clear C,V) Rd[31:0] <- SPSR_[31:0]
3-21
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-12. The multiply and multiply-accumulate instructions use an 8 bit Booth's algorithm to perform integer multiplication.
31 Cond
28 27
22 21 20 19 AS Rd
16 15 Rn
12 11 Rs
87
43 Rm
0
000000
1001
[15:12][11:8][3:0] Operand Registers [19:16] Destination Register [20] Set Condition Code
0 = Do not after condition codes 1 = Set condition codes
[21] Accumulate
0 = Multiply only 1 = Multiply and accumulate
[31:28] Condition Field
Figure 3-12. Multiply Instructions The multiply form of the instruction gives Rd:=Rm*Rs. Rn is ignored, and should be set to zero for compatibility with possible future upgrades to the instruction set. The multiply-accumulate form gives Rd:=Rm*Rs+Rn, which can save an explicit ADD instruction in some circumstances. Both forms of the instruction work on operands which may be considered as signed (2's complement) or unsigned integers. The results of a signed multiply and of an unsigned multiply of 32 bit operands differ only in the upper 32 bits - the low 32 bits of the signed and unsigned results are identical. As these instructions only produce the low 32 bits of a multiply, they can be used for both signed and unsigned multiplies. For example consider the multiplication of the operands: Operand A Operand B Result 0xFFFFFFF6 0x0000001 0xFFFFFF38
3-22
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
If the Operands Are Interpreted as Signed Operand A has the value -10, operand B has the value 20, and the result is -200 which is correctly represented as 0xFFFFFF38. If the Operands Are Interpreted as Unsigned Operand A has the value 4294967286, operand B has the value 20 and the result is 85899345720, which is represented as 0x13FFFFFF38, so the least significant 32 bits are 0xFFFFFF38. Operand Restrictions The destination register Rd must not be the same as the operand register Rm. R15 must not be used as an operand or as the destination register. All other register combinations will give correct results, and Rd, Rn and Rs may use the same register when required.
3-23
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z (Zero) flags are set correctly on the result (N is made equal to bit 31 of the result, and Z is set if and only if the result is zero). The C (Carry) flag is set to a meaningless value and the V (oVerflow) flag is unaffected.
INSTRUCTION CYCLE TIMES MUL takes 1S + mI and MLA 1S + (m+1)I cycles to execute, where S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively. m The number of 8 bit multiplier array cycles is required to complete the multiply, which is controlled by the value of the multiplier operand specified by Rs. Its possible values are as follows If bits [32:8] of the multiplier operand are all zero or all one. If bits [32:16] of the multiplier operand are all zero or all one. If bits [32:24] of the multiplier operand are all zero or all one. In all other cases.
1 2 3 4
ASSEMBLER SYNTAX MUL{cond}{S} Rd,Rm,Rs MLA{cond}{S} Rd,Rm,Rs,Rn {cond} {S} Rd, Rm, Rs and Rn Two-character condition mnemonic. See Table 3-2.. Set condition codes if S present Expressions evaluating to a register number other than R15.
EXAMPLES MUL MLAEQS R1,R2,R3 R1,R2,R3,R4 ; R1:=R2*R3 ; Conditionally R1:=R2*R3+R4, Setting condition codes.
3-24
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL, MLAL)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-13. The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results. Signed and unsigned multiplication each with optional accumulate give rise to four variations.
31 Cond
28 27
23 22 21 20 19 UAS RdHi
16 15 RdLo
12 11 Rs
87
43 Rm
0
00001
1001
[11:8][3:0] Operand Registers [19:16][15:12] Source Destination Registers [20] Set Condition Code
0 = Do not alter condition codes 1 = Set condition codes
[21] Accumulate
0 = Multiply only 1 = Multiply and accumulate
[22] Unsigned
0 = Unsigned 1 = Signed
[31:28] Condition Field
Figure 3-13. Multiply Long Instructions The multiply forms (UMULL and SMULL) take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdHi,RdLo := Rm * Rs. The lower 32 bits of the 64 bit result are written to RdLo, the upper 32 bits of the result are written to RdHi. The multiply-accumulate forms (UMLAL and SMLAL) take two 32 bit numbers, multiply them and add a 64 bit number to produce a 64 bit result of the form RdHi,RdLo := Rm * Rs + RdHi,RdLo. The lower 32 bits of the 64 bit number to add is read from RdLo. The upper 32 bits of the 64 bit number to add is read from RdHi. The lower 32 bits of the 64 bit result are written to RdLo. The upper 32 bits of the 64 bit result are written to RdHi. The UMULL and UMLAL instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result. The SMULL and SMLAL instructions treat all of their operands as two's-complement signed numbers and write a two's-complement signed 64 bit result.
3-25
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
OPERAND RESTRICTIONS * * R15 must not be used as an operand or as a destination register. RdHi, RdLo, and Rm must all specify different registers.
CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N and Z flags are set correctly on the result (N is equal to bit 63 of the result, Z is set if and only if all 64 bits of the result are zero). Both the C and V flags are set to meaningless values.
INSTRUCTION CYCLE TIMES MULL takes 1S + (m+1)I and MLAL 1S + (m+2)I cycles to execute, where m is the number of 8 bit multiplier array cycles required to complete the multiply, which is controlled by the value of the multiplier operand specified by Rs. Its possible values are as follows: For Signed INSTRUCTIONS SMULL, SMLAL:
* * * *
If bits [31:8] of the multiplier operand are all zero or all one. If bits [31:16] of the multiplier operand are all zero or all one. If bits [31:24] of the multiplier operand are all zero or all one. In all other cases.
For Unsigned Instructions UMULL, UMLAL:
* * * *
If bits [31:8] of the multiplier operand are all zero. If bits [31:16] of the multiplier operand are all zero. If bits [31:24] of the multiplier operand are all zero. In all other cases.
S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively.
3-26
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
ASSEMBLER SYNTAX Table 3-5. Assembler Syntax Descriptions Mnemonic UMULL{cond}{S} RdLo,RdHi,Rm,Rs UMLAL{cond}{S} RdLo,RdHi,Rm,Rs SMULL{cond}{S} RdLo,RdHi,Rm,Rs SMLAL{cond}{S} RdLo,RdHi,Rm,Rs where: {cond} {S} RdLo, RdHi, Rm, Rs EXAMPLES UMULL UMLALS R1,R4,R2,R3 R1,R5,R2,R3 ; R4,R1:=R2*R3 ; R5,R1:=R2*R3+R5,R1 also setting condition codes Two-character condition mnemonic. See Table 3-2. Set condition codes if S present Expressions evaluating to a register number other than R15. Description Unsigned Multiply Long Unsigned Multiply & Accumulate Long Signed Multiply Long Signed Multiply & Accumulate Long Purpose 32 x 32 = 64 32 x 32 + 64 = 64 32 x 32 = 64 32 x 32 + 64 = 64
3-27
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
SINGLE DATA TRANSFER (LDR, STR)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-14. The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. The result of this calculation may be written back into the base register if auto-indexing is required.
31 Cond 28 27 26 25 24 23 22 21 20 19 01 I PUBWL Rn 16 15 Rd 12 11 Offset 0
[15:12] Source/Destination Registers [19:16] Base Register [20] Load/Store Bit
0 = Store to memory 1 = Load from memory
[21] Write-back Bit
0 = No write-back 1 = Write address into base
[22] Byte/Word Bit
0 = Transfer word quantity 1 = Transfer byte quantity
[23] Up/Down Bit
0 = Down: subtract offset from base 1 = Up: add offset to base
[24] Pre/Post Indexing Bit
0 = Post: add offset after transfer 1 = Pre: add offset before transfer
[25] Immediate Offset
0 = Offset is an immediate value
[11:0] Offset
11 Immediate [11:0] Unsigned 12-bit immediate offset 11 Shift 43 Rm 0 0
[3:0] Offset register [11:4] Shift applied to Rm
[31:28] Condition Field Figure 3-14. Single Data Transfer Instructions
3-28
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
OFFSETS AND AUTO-INDEXING The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). The offset may be added to (U=1) or subtracted from (U=0) the base register Rn. The offset modification may be performed either before (pre-indexed, P=1) or after (post-indexed, P=0) the base is used as the transfer address. The W bit gives optional auto increment and decrement addressing modes. The modified base value may be written back into the base (W=1), or the old base value may be kept (W=0). In the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained by setting the offset to zero. Therefore post-indexed data transfers always write back the modified base. The only use of the W bit in a postindexed data transfer is in privileged mode code, where setting the W bit forces non-privileged mode for the transfer, allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware. SHIFTED REGISTER OFFSET The 8 shift control bits are described in the data processing instructions section. However, the register specified shift amounts are not available in this instruction class. See Figure 3-5. BYTES AND WORDS This instruction class may be used to transfer a byte (B=1) or a word (B=0) between an ARM920T register and memory. The action of LDR(B) and STR(B) instructions is influenced by the BIGEND control signal of ARM920T core. The two possible configurations are described below. Little-Endian Configuration A byte load (LDRB) expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary, on data bus inputs 15 through 8 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the destination register, and the remaining bits of the register are filled with zeros. Please see Figure 2-2. A byte store (STRB) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. The external memory system should activate the appropriate byte subsystem to store the data. A word load (LDR) will normally use a word aligned address. However, an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7. This means that halfwords accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the register. Two shift operations are then required to clear or to sign extend the upper 16 bits. A word store (STR) should generate a word aligned address. The word presented to the data bus is not affected if the address is not word aligned. That is, bit 31 of the register being stored always appears on data bus output 31.
3-29
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
memory A A+3 B A+2 C A+1 D A 0 8 16 24
register A 24 B 16 C 8 D 0
LDR from word aligned address memory A A+3 B A+2 A+1 A C D 0 LDR from address offset by 2 16 8 C D 0 24 B 16 8 register A 24
Figure 3-15. Little-Endian Offset Addressing Big-Endian Configuration A byte load (LDRB) expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary, on data bus inputs 23 through 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros. Please see Figure 2-1. A byte store (STRB) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. The external memory system should activate the appropriate byte subsystem to store the data. A word load (LDR) should generate a word aligned address. An address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24. This means that half-words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register. A shift operation is then required to move (and optionally sign extend) the data into the bottom 16 bits. An address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8. A word store (STR) should generate a word aligned address. The word presented to the data bus is not affected if the address is not word aligned. That is, bit 31 of the register being stored always appears on data bus output 31.
3-30
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
USE OF R15 Write-back must not be specified if R15 is specified as the base register (Rn). When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction. R15 must not be specified as the register offset (Rm). When R15 is the source register (Rd) of a register store (STR) instruction, the stored value will be address of the instruction plus 12. Restriction on the use of base register When configured for late aborts, the following example code is difficult to unwind as the base register, Rn, gets updated before the abort handler starts. Sometimes it may be impossible to calculate the initial value. After an abort, the following example code is difficult to unwind as the base register, Rn, gets updated before the abort handler starts. Sometimes it may be impossible to calculate the initial value.
EXAMPLE: LDR R0,[R1],R1
Therefore a post-indexed LDR or STR where Rm is the same register as Rn should not be used.
DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system. For instance, in a system which uses virtual memory the required data may be absent from main memory. The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued.
INSTRUCTION CYCLE TIMES Normal LDR instructions take 1S + 1N + 1I and LDR PC take 2S + 2N +1I incremental cycles, where S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STR instructions take 2N incremental cycles to execute.
3-31
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
ASSEMBLER SYNTAX {cond}{B}{T} Rd,

where: LDR STR {cond} {B} {T} Load from memory into a register Store from a register into memory Two-character condition mnemonic. See Table 3-2. If B is present then byte transfer, otherwise word transfer If T is present the W bit will be set in a post-indexed instruction, forcing non-privileged mode for the transfer cycle. T is not allowed when a pre-indexed addressing mode is specified or implied. An expression evaluating to a valid register number. Expressions evaluating to a register number. If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM920T pipelining. In this case base write-back should not be specified.
Rd Rn and Rm

LDR STR {cond} H SB SH Rd

can be: 1 An expression which generates an address: The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression. This will be a PC relative, pre-indexed address. If the address is out of range, an error will be generated. A pre-indexed addressing specification: [Rn] [Rn,<#expression>]{!} [Rn,{+/-}Rm]{!} Load from memory into a register Store from a register into memory Two-character condition mnemonic. See Table 3-2.. Transfer halfword quantity Load sign extended byte (Only valid for LDR) Load sign extended halfword (Only valid for LDR) An expression evaluating to a valid register number.
2
offset of zero offset of bytes offset of +/- contents of index register
3
A post-indexed addressing specification: [Rn],<#expression> offset of bytes [Rn],{+/-}Rm offset of +/- contents of index register. Rn and Rm are expressions evaluating to a register number. If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM920T pipelining. In this case base write-back should not be specified. Writes back the base register (set the W bit) if ! is present.
4
{!}
3-38
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
EXAMPLES LDRH R1,[R2,-R3]! ; ; ; ; ; ; ; ; ; Load R1 from the contents of the halfword address contained in R2-R3 (both of which are registers) and write back address to R2 Store the halfword in R3 at R14+14 but don't write back. Load R8 with the sign extended contents of the byte address contained in R2 and write back R2-223 to R2. Conditionally load R11 with the sign extended contents of the halfword address contained in R0. Generate PC relative offset to address FRED. Store the halfword in R5 at address FRED
STRH LDRSB LDRNESH HERE STRH FRED
R3,[R4,#14] R8,[R2],#-223 R11,[R0]
R5, [PC,#(FRED-HERE-8)];
3-39
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
BLOCK DATA TRANSFER (LDM, STM)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-18. Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible registers. They support all possible stacking modes, maintaining full or empty stacks which can grow up or down memory, and are very efficient instructions for saving or restoring context, or for moving large blocks of data around main memory.
THE REGISTER LIST The instruction can cause the transfer of any registers in the current bank (and non-user mode programs can also transfer to and from the user bank, see below). The register list is a 16 bit field in the instruction, with each bit corresponding to a register. A 1 in bit 0 of the register field will cause R0 to be transferred, a 0 will cause it not to be transferred; similarly bit 1 controls the transfer of R1, and so on. Any subset of the registers, or all the registers, may be specified. The only restriction is that the register list should not be empty. Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12.
31 Cond
28 27 100
25 24 23 22 21 20 19 PUSWL Rn
16 15 Register list
0
[19:16] Base Register [20] Load/Store Bit
0 = Store to memory 1 = Load from memory
[21] Write-back Bit
0 = No write-back 1 = Write address into base
[22] PSR & Force User Bit
0 = Do not load PSR or user mode 1 = Load PSR or force user mode
[23] Up/Down Bit
0 = Down: subtract offset from base 1 = Up: add offset to base
[24] Pre/Post Indexing Bit
0 = Post: add offset after transfer 1 = Pre: add offset bofore transfer
[31:28] Condition Field Figure 3-18. Block Data Transfer Instructions
3-40
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
ADDRESSING MODES The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the up/ down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last. The lowest register also gets transferred to/from the lowest memory address. By way of illustration, consider the transfer of R1, R5 and R7 in the case where Rn=0x1000 and write back of the modified base is required (W=1). Figure 3.19-22 show the sequence of register transfers, the addresses used, and the value of Rn after the instruction has completed. In all cases, had write back of the modified base not been required (W=0), Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction, when it would have been overwritten with the loaded value.
ADDRESS ALIGNMENT The address should normally be a word aligned quantity and non-word aligned addresses do not affect the instruction. However, the bottom 2 bits of the address will appear on A[1:0] and might be interpreted by the memory system.
0x100C
0x100C
Rn
0x1000
R1
0x1000
0x0FF4 1 0x100C R5 R1 Rn R7 R5 R1 2
0x0FF4
0x100C
0x1000
0x1000
0x0FF4 3 4
0x0FF4
Figure 3-19. Post-Increment Addressing
3-41
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
0x100C R1 Rn 0x1000
0x100C
0x1000
0x0FF4 1 0x100C R5 R1 0x1000 Rn 2 R7 R5 R1
0x0FF4
0x100C
0x1000
0x0FF4 3 4
0x0FF4
Figure 3-20. Pre-Increment Addressing
0x100C
0x100C
Rn
0x1000 R1 0x0FF4 1 0x100C 2
0x1000
0x0FF4
0x100C
0x1000 R5 R1 0x0FF4 3 Rn
R7 R5 R1
0x1000
0x0FF4 4
Figure 3-21. Post-Decrement Addressing
3-42
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
0x100C
0x100C
Rn
0x1000
0x1000
0x0FF4 1 0x100C
R1 2
0x0FF4
0x100C
0x1000 R5 R1 3 R7 R5 R1 4
0x1000
0x0FF4
Rn
0x0FF4
Figure 3-22. Pre-Decrement Addressing USE OF THE S BIT When the S bit is set in a LDM/STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction. The S bit should only be set if the instruction is to execute in a privileged mode. LDM with R15 in Transfer List and S Bit Set (Mode Changes) If the instruction is a LDM then SPSR_ is transferred to CPSR at the same time as R15 is loaded. STM with R15 in Transfer List and S Bit Set (User Bank Transfer) The registers transferred are taken from the User bank rather than the bank corresponding to the current mode. This is useful for saving the user state on process switches. Base write-back should not be used when this mechanism is employed. R15 not in List and S Bit Set (User Bank Transfer) For both LDM and STM instructions, the User bank registers are transferred rather than the register bank corresponding to the current mode. This is useful for saving the user state on process switches. Base write-back should not be used when this mechanism is employed. When the instruction is LDM, care must be taken not to read from a banked register during the following cycle (inserting a dummy instruction such as MOV R0, R0 after the LDM will ensure safety). USE OF R15 AS THE BASE R15 should not be used as the base register in any LDM or STM instruction.
3-43
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
INCLUSION OF THE BASE IN THE REGISTER LIST When write-back is specified, the base is written back at the end of the second cycle of the instruction. During a STM, the first register is written out at the start of the second cycle. A STM which includes storing the base, with the base as the first register to be stored, will therefore store the unchanged value, whereas with the base second or later in the transfer order, will store the modified value. A LDM will always overwrite the updated base if the base is in the list. DATA ABORTS Some legal addresses may be unacceptable to a memory management system, and the memory manager can indicate a problem with an address by taking the ABORT signal HIGH. This can happen on any transfer during a multiple register load or store, and must be recoverable if ARM920T is to be used in a virtual memory system. Abort during STM Instructions If the abort occurs during a store multiple instruction, ARM920T takes little action until the instruction completes, whereupon it enters the data abort trap. The memory manager is responsible for preventing erroneous writes to the memory. The only change to the internal state of the processor will be the modification of the base register if writeback was specified, and this must be reversed by software (and the cause of the abort resolved) before the instruction may be retried. Aborts during LDM Instructions When ARM920T detects a data abort during a load multiple instruction, it modifies the operation of the instruction to ensure that recovery is possible. * * Overwriting of registers stops when the abort happens. The aborting load will not take place but earlier ones may have overwritten registers. The PC is always the last register to be written and so will always be preserved. The base register is restored, to its modified value if write-back was requested. This ensures recoverability in the case where the base register is also in the transfer list, and may have been overwritten before the abort occurred.
The data abort trap is taken when the load multiple has completed, and the system software must undo any base modification (and resolve the cause of the abort) before restarting the instruction.
INSTRUCTION CYCLE TIMES Normal LDM instructions take nS + 1N + 1I and LDM PC takes (n+1)S + 2N + 1I incremental cycles, where S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STM instructions take (n-1)S + 2N incremental cycles to execute, where n is the number of words transferred.
3-44
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
ASSEMBLER SYNTAX {cond} Rn{!},{^} where: {cond} Rn {!} {^} Two character condition mnemonic. See Table 3-2. An expression evaluating to a valid register number A list of registers and register ranges enclosed in {} (e.g. {R0,R2-R7,R10}). If present requests write-back (W=1), otherwise W=0. If present set S bit to load the CPSR along with the PC, or force transfer of user bank when in privileged mode.
Addressing Mode Names There are different assembler mnemonics for each of the addressing modes, depending on whether the instruction is being used to support stacks or for other purposes. The equivalence between the names and the values of the bits in the instruction are shown in the following table 3-6. Table 3-6. Addressing Mode Names Name Pre-Increment Load Post-Increment Load Pre-Decrement Load Post-Decrement Load Pre-Increment Store Post-Increment Store Pre-Decrement Store Post-Decrement Store Stack LDMED LDMFD LDMEA LDMFA STMFA STMEA STMFD STMED Other LDMIB LDMIA LDMDB LDMDA STMIB STMIA STMDB STMDA L bit 1 1 1 1 0 0 0 0 P bit 1 0 1 0 1 0 1 0 U bit 1 1 0 0 1 1 0 0
FD, ED, FA, EA define pre/post indexing and the up/down bit by reference to the form of stack required. The F and E refer to a "full" or "empty" stack, i.e. whether a pre-index has to be done (full) before storing to the stack. The A and D refer to whether the stack is ascending or descending. If ascending, a STM will go up and LDM down, if descending, vice-versa. IA, IB, DA, DB allow control when LDM/STM are not being used for stacks and simply mean Increment After, Increment Before, Decrement After, Decrement Before.
3-45
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
EXAMPLES LDMFD STMIA LDMFD LDMFD STMFD SP!,{R0,R1,R2} R0,{R0-R15} SP!,{R15} SP!,{R15}^ R13,{R0-R14}^ ; ; ; ; ; ; ; Unstack 3 registers. Save all registers. R15 (SP), CPSR unchanged. R15 (SP), CPSR <- SPSR_mode (allowed only in privileged modes). Save user mode regs on stack (allowed only in privileged modes).
These instructions may be used to save state on subroutine entry, and restore it efficiently on return to the calling routine: STMED BL LDMED SP!,{R0-R3,R14} somewhere SP!,{R0-R3,R15} ; ; ; ; Save R0 to R3 to use as workspace and R14 for returning. This nested call will overwrite R14 Restore workspace and return.
3-46
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
SINGLE DATA SWAP (SWP)
31 Cond
28 27 00010
23 22 21 20 19 B 00 Rn
16 15 Rd
12 11 0000
87 1001
43 Rm
0
[3:0] Source Register [15:12] Destination Register [19:16] Base Register [22] Byte/Word Bit
0 = Swap word quantity 1 = Swap word quantity
[31:28] Condition Field
Figure 3-23. Swap Instruction The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-23. The data swap instruction is used to swap a byte or word quantity between a register and external memory. This instruction is implemented as a memory read followed by a memory write which are "locked" together (the processor cannot be interrupted until both operations have completed, and the memory manager is warned to treat them as inseparable). This class of instruction is particularly useful for implementing software semaphores. The swap address is determined by the contents of the base register (Rn). The processor first reads the contents of the swap address. Then it writes the contents of the source register (Rm) to the swap address, and stores the old memory contents in the destination register (Rd). The same register may be specified as both the source and destination. The LOCK output goes HIGH for the duration of the read and write operations to signal to the external memory manager that they are locked together, and should be allowed to complete without interruption. This is important in multi-processor systems where the swap instruction is the only indivisible instruction which may be used to implement semaphores; control of the memory must not be removed from a processor while it is performing a locked operation.
BYTES AND WORDS This instruction class may be used to swap a byte (B=1) or a word (B=0) between an ARM920T register and memory. The SWP instruction is implemented as a LDR followed by a STR and the action of these is as described in the section on single data transfers. In particular, the description of Big and Little Endian configuration applies to the SWP instruction.
3-47
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
USE OF R15 Do not use R15 as an operand (Rd, Rn or Rs) in a SWP instruction.
DATA ABORTS If the address used for the swap is unacceptable to a memory management system, the memory manager can flag the problem by driving ABORT HIGH. This can happen on either the read or the write cycle (or both), and in either case, the Data Abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued.
INSTRUCTION CYCLE TIMES Swap instructions take 1S + 2N +1I incremental cycles to execute, where S,N and I are defined as sequential (S-cycle), non-sequential, and internal (I-cycle), respectively.
ASSEMBLER SYNTAX {cond}{B} Rd,Rm,[Rn] {cond} {B} Rd,Rm,Rn Examples SWP SWPB SWPEQ R0,R1,[R2] R2,R3,[R4] R0,R0,[R1] ; ; ; ; ; ; Load R0 with the word addressed by R2, and store R1 at R2. Load R2 with the byte addressed by R4, and store bits 0 to 7 of R3 at R4. Conditionally swap the contents of the word addressed by R1 with R0. Two-character condition mnemonic. See Table 3-2. If B is present then byte transfer, otherwise word transfer Expressions evaluating to valid register numbers
3-48
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
SOFTWARE INTERRUPT (SWI)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-24, below.
31 Cond
28 27 1111
24 23 Comment Field (Ignored by Processor)
0
[31:28] Condition Field
Figure 3-24. Software Interrupt Instruction The software interrupt instruction is used to enter Supervisor mode in a controlled manner. The instruction causes the software interrupt trap to be taken, which effects the mode change. The PC is then forced to a fixed value (0x08) and the CPSR is saved in SPSR_svc. If the SWI vector address is suitably protected (by external memory management hardware) from modification by the user, a fully protected operating system may be constructed.
RETURN FROM THE SUPERVISOR The PC is saved in R14_svc upon entering the software interrupt trap, with the PC adjusted to point to the word after the SWI instruction. MOVS PC,R14_svc will return to the calling program and restore the CPSR. Note that the link mechanism is not re-entrant, so if the supervisor code wishes to use software interrupts within itself it must first save a copy of the return address and SPSR.
COMMENT FIELD The bottom 24 bits of the instruction are ignored by the processor, and may be used to communicate information to the supervisor code. For instance, the supervisor may look at this field and use it to index into an array of entry points for routines which perform the various supervisor functions.
INSTRUCTION CYCLE TIMES Software interrupt instructions take 2S + 1N incremental cycles to execute, where S and N are defined as sequential (S-cycle) and non-sequential (N-cycle).
3-49
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
ASSEMBLER SYNTAX SWI{cond} {cond} Examples SWI SWI SWINE Supervisor code The previous examples assume that suitable supervisor code exists, for instance: 0x08 B Supervisor EntryTable DCD ZeroRtn DCD ReadCRtn DCD WriteIRtn
***
Two character condition mnemonic, Table 3-2. Evaluated and placed in the comment field (which is ignored by ARM920T).
ReadC WriteI+"k" 0
; Get next character from read stream. ; Output a "k" to the write stream. ; Conditionally call supervisor with 0 in comment field.
; SWI entry point ; Addresses of supervisor routines
ReadC WriteI
Zero EQU 256 EQU 512 Supervisor STMFD LDR BIC MOV ADR LDR WriteIRtn
***
EQU 0
R13,{R0-R2,R14} R0,[R14,#-4] R0,R0,#0xFF000000 R1,R0,LSR#8 R2,EntryTable R15,[R2,R1,LSL#2]
; ; ; ; ; ; ; ; ;
SWI has routine required in bits 8-23 and data (if any) in bits 0-7. Assumes R13_svc points to a suitable stack Save work registers and return address. Get SWI instruction. Clear top 8 bits. Get routine offset. Get start address of entry table. Branch to appropriate routine. Enter with character in R0 bits 0-7.
LDMFD
R13,{R0-R2,R15}^
; Restore workspace and return, ; restoring processor mode and flags.
3-50
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
COPROCESSOR DATA OPERATIONS (CDP)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-25. This class of instruction is used to tell a coprocessor to perform some internal operation. No result is communicated back to ARM920T, and it will not wait for the operation to complete. The coprocessor could contain a queue of such instructions awaiting execution, and their execution can overlap other activity, allowing the coprocessor and ARM920T to perform independent tasks in parallel.
COPROCESSOR INSTRUCTIONS The S3C44B0X, unlike some other ARM-based processors, does not have an external coprocessor interface. It does not have a on-chip coprocessor also. So then all coprocessor instructions will cause the undefined instruction trap to be taken on the S3C44B0X. These coprocessor instructions can be emulated by the undefined trap handler. Even though external coprocessor can not be connected to the S3C44B0X, the coprocessor instructions are still described here in full for completeness. (Remember that any external coprocessor described in this section is a software emulation.)
31 Cond
28 27 1110
24 23 CP Opc
20 19 CRn
16 15 CRd
12 11 Cp#
87 Cp
543 0 CRm
0
[3:0] Coprocessor operand register [7:5] Coprocessor information [11:8] Coprocessor number [15:12] Coprocessor destination register [19:16] Coprocessor operand register [23:20] Coprocessor operation code [31:28] Condition Field Figure 3-25. Coprocessor Data Operation Instruction Only bit 4 and bits 24 to 31 The coprocessor fields are significant to ARM920T. The remaining bits are used by coprocessors. The above field names are used by convention, and particular coprocessors may redefine the use of all fields except CP# as appropriate. The CP# field is used to contain an identifying number (in the range 0 to 15) for each coprocessor, and a coprocessor will ignore any instruction which does not contain its number in the CP# field. The conventional interpretation of the instruction is that the coprocessor should perform an operation specified in the CP Opc field (and possibly in the CP field) on the contents of CRn and CRm, and place the result in CRd.
3-51
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S + bI incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. S and I are defined as sequential (S-cycle) and internal (I-cycle). Assembler syntax CDP{cond} p#,,cd,cn,cm{,} {cond} p# cd, cn and cm EXAMPLES CDP CDPEQ p1,10,c1,c2,c3 p2,5,c1,c2,c3,2 ; ; ; ; Request coproc 1 to do operation 10 on CR2 and CR3, and put the result in CR1. If Z flag is set request coproc 2 to do operation 5 (type 2) on CR2 and CR3, and put the result in CR1. Two character condition mnemonic. See Table 3-2. The unique number of the required coprocessor Evaluated to a constant and placed in the CP Opc field Evaluate to the valid coprocessor register numbers CRd, CRn and CRm respectively Where present is evaluated to a constant and placed in the CP field
3-52
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
COPROCESSOR DATA TRANSFERS (LDC, STC)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-26. This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessors's registers directly to memory. ARM920T is responsible for supplying the memory address, and the coprocessor supplies or accepts the data and controls the number of words transferred.
31 Cond
28 27 110
25 24 23 22 21 20 19 PUNWL Rn
16 15 CRd
12 11 CP#
87 Offset
0
[7:0] Unsigned 8 Bit Immediate Offset [11:8] Coprocessor Number [15:12] Coprocessor Source/Destination Register [19:16] Base Register [20] Load/Store Bit
0 = Store to memory 1 = Load from memory
[21] Write-back Bit
0 = No write-back 1 = Write address into base
[22] Transfer Length [23] Up/Down Bit
0 = Down: subtract offset from base 1 = Up: add offset to base
[24] Pre/Post Indexing Bit
0 = Post: add offset after transfer 1 = Pre: add offset before transfer
[31:28] Condition Field Figure 3-26. Coprocessor Data Transfer Instructions
3-53
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
THE COPROCESSOR FIELDS The CP# field is used to identify the coprocessor which is required to supply or accept the data, and a coprocessor will only respond if its number matches the contents of this field. The CRd field and the N bit contain information for the coprocessor which may be interpreted in different ways by different coprocessors, but by convention CRd is the register to be transferred (or the first register where more than one is to be transferred), and the N bit is used to choose one of two transfer length options. For instance N=0 could select the transfer of a single register, and N=1 could select the transfer of all the registers for context switching. ADDRESSING MODES ARM920T is responsible for providing the address used by the memory system for the transfer, and the addressing modes available are a subset of those used in single data transfer instructions. Note, however, that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers, whereas they are 12 bits wide and specify byte offsets for single data transfers. The 8 bit unsigned immediate offset is shifted left 2 bits and either added to (U=1) or subtracted from (U=0) the base register (Rn); this calculation may be performed either before (P=1) or after (P=0) the base is used as the transfer address. The modified base value may be overwritten back into the base register (if W=1), or the old value of the base may be preserved (W=0). Note that post-indexed addressing modes require explicit setting of the W bit, unlike LDR and STR which always write-back when post-indexed. The value of the base register, modified by the offset in a pre-indexed instruction, is used as the address for the transfer of the first word. The second word (if more than one is transferred) will go to or come from an address one word (4 bytes) higher than the first transfer, and the address will be incremented by one word for each subsequent transfer. ADDRESS ALIGNMENT The base address should normally be a word aligned quantity. The bottom 2 bits of the address will appear on A[1:0] and might be interpreted by the memory system. Use of R15 If Rn is R15, the value used will be the address of the instruction plus 8 bytes. Base write-back to R15 must not be specified. DATA ABORTS If the address is legal but the memory manager generates an abort, the data trap will be taken. The write-back of the modified base will take place, but all other processor state will be preserved. The coprocessor is partly responsible for ensuring that the data transfer can be restarted after the cause of the abort has been resolved, and must ensure that any subsequent actions it undertakes can be repeated when the instruction is retried. Instruction cycle times Coprocessor data transfer instructions take (n-1)S + 2N + bI incremental cycles to execute, where: n b The number of words transferred. The number of cycles spent in the coprocessor busy-wait loop.
S, N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively.
3-54
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
ASSEMBLER SYNTAX {cond}{L} p#,cd,

LDC STC {L} {cond} p# cd Load from memory to coprocessor Store from coprocessor to memory When present perform long transfer (N=1), otherwise perform short transfer (N=0) Two character condition mnemonic. See Table 3-2.. The unique number of the required coprocessor An expression evaluating to a valid coprocessor register number that is placed in the CRd field can be: An expression which generates an address: The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression. This will be a PC relative, pre-indexed address. If the address is out of range, an error will be generated A pre-indexed addressing specification: [Rn] offset of zero [Rn,<#expression>]{!} offset of bytes A post-indexed addressing specification: [Rn],<#expression offset of bytes {!} write back the base register (set the W bit) if! is present Rn is an expression evaluating to a valid ARM920T register number. NOTES If Rn is R15, the assembler will subtract 8 from the offset value to allow for ARM920T pipelining. EXAMPLES LDC STCEQL p1,c2,table p2,c3,[R5,#24]! ; ; ; ; ; ; Load c2 of coproc 1 from address table, using a PC relative address. Conditionally store c3 of coproc 2 into an address 24 bytes up from R5, write this address back to R5, and use long transfer option (probably to store multiple words).

1
2
3
NOTES Although the address offset is expressed in bytes, the instruction offset field is in words. The assembler will adjust the offset appropriately.
3-55
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
COPROCESSOR REGISTER TRANSFERS (MRC, MCR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.. The instruction encoding is shown in Figure 3-27. This class of instruction is used to communicate information directly between ARM920T and a coprocessor. An example of a coprocessor to ARM920T register transfer (MRC) instruction would be a FIX of a floating point value held in a coprocessor, where the floating point number is converted into a 32 bit integer within the coprocessor, and the result is then transferred to ARM920T register. A FLOAT of a 32 bit value in ARM920T register into a floating point value within the coprocessor illustrates the use of ARM920T register to coprocessor transfer (MCR). An important use of this instruction is to communicate control information directly from the coprocessor into the ARM920T CPSR flags. As an example, the result of a comparison of two floating point values within a coprocessor can be moved to the CPSR to control the subsequent flow of execution.
31 Cond
28 27 1110
24 23
21 20 19 L CRn
16 15 Rd
12 11 CP#
87 CP
543 1 CRm
0
CP Opc
[3:0] Coprocessor Operand Register [7:5] Coprocessor Information [11:8] Coprocessor Number [15:12] ARM Source/Destination Register [19:16] Coprocessor Source/Destination Register [20] Load/Store Bit
0 = Store to coprocessor 1 = Load from coprocessor
[21] Coprocessor Operation Mode [31:28] Condition Field
Figure 3-27. Coprocessor Register Transfer Instructions THE COPROCESSOR FIELDS The CP# field is used, as for all coprocessor instructions, to specify which coprocessor is being called upon. The CP Opc, CRn, CP and CRm fields are used only by the coprocessor, and the interpretation presented here is derived from convention only. Other interpretations are allowed where the coprocessor functionality is incompatible with this one. The conventional interpretation is that the CP Opc and CP fields specify the operation the coprocessor is required to perform, CRn is the coprocessor register which is the source or destination of the transferred information, and CRm is a second coprocessor register which may be involved in some way which depends on the particular operation specified.
3-56
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
TRANSFERS TO R15 When a coprocessor register transfer to ARM920T has R15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the N, Z, C and V flags respectively. The other bits of the transferred word are ignored, and the PC and other CPSR bits are unaffected by the transfer.
TRANSFERS FROM R15 A coprocessor register transfer from ARM920T with R15 as the source register will store the PC+12.
INSTRUCTION CYCLE TIMES MRC instructions take 1S + (b+1)I +1C incremental cycles to execute, where S, I and C are defined as sequential (S-cycle), internal (I-cycle), and coprocessor register transfer (C-cycle), respectively. MCR instructions take 1S + bI +1C incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop.
ASSEMBLER SYNTAX {cond} p#,,Rd,cn,cm{,} MRC MCR {cond} p# Rd cn and cm Move from coprocessor to ARM920T register (L=1) Move from ARM920T register to coprocessor (L=0) Two character condition mnemonic. See Table 3-2 The unique number of the required coprocessor Evaluated to a constant and placed in the CP Opc field An expression evaluating to a valid ARM920T register number Expressions evaluating to the valid coprocessor register numbers CRn and CRm respectively Where present is evaluated to a constant and placed in the CP field
EXAMPLES MRC p2,5,R3,c5,c6 ; ; ; ; ; ; ; ; Request coproc 2 to perform operation 5 on c5 and c6, and transfer the (single 32-bit word) result back to R3. Request coproc 6 to perform operation 0 on R4 and place the result in c6. Conditionally request coproc 3 to perform operation 9 (type 2) on c5 and c6, and transfer the result back to R3.
MCR MRCEQ
p6,0,R4,c5,c6 p3,9,R3,c5,c6,2
3-57
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
UNDEFINED INSTRUCTION The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction format is shown in Figure 3-28.
31 Cond
28 27 011
25 24 xxxxxxxxxxxxxxxxxxxx
543 1 xxxx
0
Figure 3-28. Undefined Instruction If the condition is true, the undefined instruction trap will be taken. Note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present, and all coprocessors must refuse to accept it by driving CPA and CPB HIGH.
INSTRUCTION CYCLE TIMES This instruction takes 2S + 1I + 1N cycles, where S, N and I are defined as sequential (S-cycle), non-sequential (Ncycle), and internal (I-cycle).
ASSEMBLER SYNTAX The assembler has no mnemonics for generating this instruction. If it is adopted in the future for some specified use, suitable mnemonics will be added to the assembler. Until such time, this instruction must not be used.
3-58
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
INSTRUCTION SET EXAMPLES The following examples show ways in which the basic ARM920T instructions can combine to give efficient code. None of these methods saves a great deal of execution time (although they may save some), mostly they just save code.
USING THE CONDITIONAL INSTRUCTIONS Using Conditionals for Logical OR CMP BEQ CMP BEQ This can be replaced by CMP CMPNE BEQ Absolute Value TEQ RSBMI Rn,#0 Rn,Rn,#0 ; Test sign ; and 2's complement if necessary. Rn,#p Rm,#q Label Rn,#p Label Rm,#q Label ; If Rn=p OR Rm=q THEN GOTO Label.
; If condition not satisfied try other test.
Multiplication by 4, 5 or 6 (Run Time) MOV CMP ADDCS ADDHI Rc,Ra,LSL#2 Rb,#5 Rc,Rc,Ra Rc,Rc,Ra ; ; ; ; Multiply by 4, Test value, Complete multiply by 5, Complete multiply by 6.
Combining Discrete and Range Tests TEQ CMPNE MOVLS Rc,#127 Rc,# " "-1 Rc,# "" ; ; ; ; Discrete test, Range test IF Rc<= "" OR Rc=ASCII(127) THEN Rc:= "."
3-59
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
Division and Remainder A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross Development Toolkit, available from your supplier. A short general purpose divide routine follows. ; Enter with numbers in Ra and Rb. ; Bit to control the division. ; Move Rb until greater than Ra.
Div1
Div2
MOV CMP CMPCC MOVCC MOVCC BCC MOV CMP SUBCS ADDCS MOVS MOVNE BNE
Rcnt,#1 Rb,#0x80000000 Rb,Ra Rb,Rb,ASL#1 Rcnt,Rcnt,ASL#1 Div1 Rc,#0 Ra,Rb Ra,Ra,Rb Rc,Rc,Rcnt Rcnt,Rcnt,LSR#1 Rb,Rb,LSR#1 Div2
; ; ; ; ; ;
Test for possible subtraction. Subtract if ok, Put relevant bit into result Shift control bit Halve unless finished. Divide result in Rc, remainder in Ra.
Overflow Detection in the ARM920T 1. Overflow in unsigned multiply with a 32-bit result UMULL TEQ BNE 2. Rd,Rt,Rm,Rn Rt,#0 overflow ; 3 to 6 cycles ; +1 cycle and a register
Overflow in signed multiply with a 32-bit result SMULL TEQ BNE Rd,Rt,Rm,Rn Rt,Rd ASR#31 overflow ; 3 to 6 cycles ; +1 cycle and a register
3.
Overflow in unsigned multiply accumulate with a 32 bit result UMLAL TEQ BNE Rd,Rt,Rm,Rn Rt,#0 overflow ; 4 to 7 cycles ; +1 cycle and a register
4.
Overflow in signed multiply accumulate with a 32 bit result SMLAL TEQ BNE Rd,Rt,Rm,Rn Rt,Rd, ASR#31 overflow ; 4 to 7 cycles ; +1 cycle and a register
3-60
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
5.
Overflow in unsigned multiply accumulate with a 64 bit result UMULL ADDS ADC BCS Rl,Rh,Rm,Rn Rl,Rl,Ra1 Rh,Rh,Ra2 overflow ; ; ; ; 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 registers
6.
Overflow in signed multiply accumulate with a 64 bit result SMULL ADDS ADC BVS Rl,Rh,Rm,Rn Rl,Rl,Ra1 Rh,Rh,Ra2 overflow ; ; ; ; 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 registers
NOTES Overflow checking is not applicable to unsigned and signed multiplies with a 64-bit result, since overflow does not occur in such calculations.
PSEUDO-RANDOM BINARY SEQUENCE GENERATOR It is often necessary to generate (pseudo-) random numbers and the most efficient algorithms are based on shift generators with exclusive-OR feedback rather like a cyclic redundancy check generator. Unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal length (i.e. 2^32-1 cycles before repetition), so this example uses a 33 bit register with taps at bits 33 and 20. The basic algorithm is newbit:=bit 33 eor bit 20, shift left the 33 bit number and put in newbit at the bottom; this operation is performed for all the newbits needed (i.e. 32 bits). The entire operation can be done in 5 S cycles: ; ; ; ; ; ; ; Enter with seed in Ra (32 bits), Rb (1 bit in Rb lsb), uses Rc. Top bit into carry 33 bit rotate right Carry into lsb of Rb (involved!) (similarly involved!) new seed in Ra, Rb as before
TST MOVS ADC EOR EOR
Rb,Rb,LSR#1 Rc,Ra,RRX Rb,Rb,Rb Rc,Rc,Ra,LSL#12 Ra,Rc,Rc,LSR#20
MULTIPLICATION BY CONSTANT USING THE BARREL SHIFTER Multiplication by 2^n (1,2,4,8,16,32..) MOV Ra, Rb, LSL #n
Multiplication by 2^n+1 (3,5,9,17..) ADD Ra,Ra,Ra,LSL #n
Multiplication by 2^n-1 (3,7,15..) RSB Ra,Ra,Ra,LSL #n
3-61
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
Multiplication by 6 ADD MOV Ra,Ra,Ra,LSL #1 Ra,Ra,LSL#1 ; Multiply by 3 ; and then by 2
Multiply by 10 and add in extra number ADD ADD Ra,Ra,Ra,LSL#2 Ra,Rc,Ra,LSL#1 ; Multiply by 5 ; Multiply by 2 and add in next digit
General recursive method for Rb := Ra*C, C a constant: 1. If C even, say C = 2^n*D, D odd: D=1: D<>1: MOV MOV Rb,Ra,LSL #n {Rb := Ra*D} Rb,Rb,LSL #n
2. If C MOD 4 = 1, say C = 2^n*D+1, D odd, n>1: D=1: D<>1: ADD ADD Rb,Ra,Ra,LSL #n {Rb := Ra*D} Rb,Ra,Rb,LSL #n
3. If C MOD 4 = 3, say C = 2^n*D-1, D odd, n>1: D=1: D<>1: RSB RSB Rb,Ra,Ra,LSL #n {Rb := Ra*D} Rb,Ra,Rb,LSL #n
This is not quite optimal, but close. An example of its non-optimality is multiply by 45 which is done by: RSB RSB ADD rather than by: ADD ADD Rb,Ra,Ra,LSL#3 Rb,Rb,Rb,LSL#2 ; Multiply by 9 ; Multiply by 5*9 = 45 Rb,Ra,Ra,LSL#2 Rb,Ra,Rb,LSL#2 Rb,Ra,Rb,LSL# 2 ; Multiply by 3 ; Multiply by 4*3-1 = 11 ; Multiply by 4*11+1 = 45
3-62
S3C2400 RISC MICROPROCESSOR
ARM INSTRUCTION SET
LOADING A WORD FROM AN UNKNOWN ALIGNMENT ; ; ; ; ; ; ; ; ; Enter with address in Ra (32 bits) uses Rb, Rc result in Rd. Note d must be less than c e.g. 0,1 Get word aligned address Get 64 bits containing answer Correction factor in bytes ...now in bits and test if aligned Produce bottom of result word (if not aligned) Get other shift amount Combine two halves to get result
BIC LDMIA AND MOVS MOVNE RSBNE ORRNE
Rb,Ra,#3 Rb,{Rd,Rc} Rb,Ra,#3 Rb,Rb,LSL#3 Rd,Rd,LSR Rb Rb,Rb,#32 Rd,Rd,Rc,LSL Rb
3-63
ARM INSTRUCTION SET
S3C2400 RISC MICROPROCESSOR
NOTES
3-64
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
4
THUMB INSTRUCTION SET
THUMB INSTRUCTION SET FORMAT
The thumb instruction sets are 16-bit versions of ARM instruction sets (32-bit format). The ARM instructions are reduced to 16-bit versions, Thumb instructions, at the cost of versatile functions of the ARM instruction sets. The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM920T core. As the Thumb instructions are compressed ARM instructions, the Thumb instructions have the 16-bit format instructions and have some restrictions. The restrictions by 16-bit format is fully notified for using the Thumb instructions.
4-1
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure.
15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 B 0 1 0 1 1 0 1 1 0 1 1 0 H 1 Op 0 0 1 L H L L L SP 0 L L 0 1 B S 0 1 Op 1 I
9
8 Offset5
7
6
5
4 Rs Rs
3
2
1 Rd Rd
0 Move Shifted register Add/subtract Move/compare/add/ subtract immediate
Op Rd
Rn/offset3
Offset8 Op Rs Rs/Hs Word8 Ro Ro Rb Rb Rb Rb Word8 Word8 0 R S SWord7 Rlist Rlist Softset8 1 Value8 Offset11 Offset Rd Rd Rd Rd Rd Rd/Hd
ALU operations Hi register operations /branch exchange PC-relative load Load/store with register offset Load/store sign-extended byte/halfword Load/store with immediate offset Load/store halfword SP-relative load/store Load address Add offset to stack pointer Push/pop register Multiple load/store Conditional branch Software interrupt Unconditional branch Long branch with link
Op Rd 0 1
H1 H2
Offset5 Offset5 Rd Rd 0 0 Rb Cond 1 1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Figure 4-1. THUMB Instruction Set Formats
4-2
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
OPCODE SUMMARY The following table summarizes the THUMB instruction set. For further information about a particular instruction please refer to the sections listed in the right-most column. Table 4-1. THUMB Instruction Set Opcodes Mnemonic ADC ADD AND ASR B Bxx BIC BL BX CMN CMP EOR LDMIA LDR LDRB LDRH LSL LDSB LDSH LSR MOV MUL MVN Add with Carry Add AND Arithmetic Shift Right Unconditional branch Conditional branch Bit Clear Branch and Link Branch and Exchange Compare Negative Compare EOR Load multiple Load word Load byte Load halfword Logical Shift Left Load sign-extended byte Load sign-extended halfword Logical Shift Right Move register Multiply Move Negative register Instruction Lo-Register Operand Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Hi-Register Operand Y Y Y Condition Codes Set Y Y(1) Y Y Y Y Y Y Y Y Y(2) Y Y
4-3
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
Table 4-1. THUMB Instruction Set Opcodes (Continued) Mnemonic NEG ORR POP PUSH ROR SBC STMIA STR STRB STRH SWI SUB TST Negate OR Pop register Push register Rotate Right Subtract with Carry Store Multiple Store word Store byte Store halfword Software Interrupt Subtract Test bits Instruction Lo-Register Operand Y Y Y Y Y Y Y Y Y Y Y Y Hi-Register Operand Condition Codes Set Y Y Y Y Y Y
NOTES: 1. The condition codes are unaffected by the format 5, 12 and 13 versions of this instruction. 2. The condition codes are unaffected by the format 5 version of this instruction.
4-4
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
FORMAT 1: MOVE SHIFTED REGISTER
15 0
14 0
13 0
12 Op
11
10 Offset5
6
5 Rs
3
2 Rd
0
[2:0] Destination Register [5:3] Source Register [10:6] Immediate Vale [12:11] Opcode
0 = LSL 1 = LSR 2 = ASR
Figure 4-2. Format 1 OPERATION These instructions move a shifted value between Lo registers. The THUMB assembler syntax is shown in Table 4-2. NOTE All instructions in this group set the CPSR condition codes.
Table 4-2. Summary of Format 1 Instructions OP 00 01 THUMB Assembler LSL Rd, Rs, #Offset5 LSR Rd, Rs, #Offset5 ARM Equipment MOVS Rd, Rs, LSL #Offset5 MOVS Rd, Rs, LSR #Offset5 Action Shift Rs left by a 5-bit immediate value and store the result in Rd. Perform logical shift right on Rs by a 5-bit immediate value and store the result in Rd. Perform arithmetic shift right on Rs by a 5-bit immediate value and store the result in Rd.
10
ASR Rd, Rs, #Offset5
MOVS Rd, Rs, ASR #Offset5
4-5
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-2. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LSR R2, R5, #27 ; Logical shift right the contents ; of R5 by 27 and store the result in R2. ; Set condition codes on the result.
4-6
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
FORMAT 2: ADD/SUBTRACT
15 0
14 0
13 0
12 1
11 1
10 1
9 Op
8 Rn/Offset3
6
5 Rs
3
2 Rd
0
[2:0] Destination Register [5:3] Source Register [8:6] Register/Immediate Vale [9] Opcode
0 = ADD 1 = SUB
[10] Immediate Flag
0 = Register operand 1 = Immediate oerand
Figure 4-3. Format 2
OPERATION These instructions allow the contents of a Lo register or a 3-bit immediate value to be added to or subtracted from a Lo register. The THUMB assembler syntax is shown in Table 4-3. NOTE All instructions in this group set the CPSR condition codes.
Table 4-3. Summary of Format 2 Instructions OP 0 0 1 1 I 0 1 0 1 THUMB Assembler ADD Rd, Rs, Rn ADD Rd, Rs, #Offset3 SUB Rd, Rs, Rn SUB Rd, Rs, #Offset3 ARM Equipment ADDS Rd, Rs, Rn ADDS Rd, Rs, #Offset3 SUBS Rd, Rs, Rn SUBS Rd, Rs, #Offset3 Action Add contents of Rn to contents of Rs. Place result in Rd. Add 3-bit immediate value to contents of Rs. Place result in Rd. Subtract contents of Rn from contents of Rs. Place result in Rd. Subtract 3-bit immediate value from contents of Rs. Place result in Rd.
4-7
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-3. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD SUB R0, R3, R4 R6, R2, #6 ; R0 := R3 + R4 and set condition codes on the result. ; R6 := R2 - 6 and set condition codes.
4-8
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE
15 0
14 0
13 0
12 Op
11
10 Rd
8
7 Offset8
0
[7:0] Immediate Vale [10:8] Source/Destination Register [12:11] Opcode
0 = MOV 1 = CMP 2 = ADD 3 = SUB
Figure 4-4. Format 3 OPERATIONS The instructions in this group perform operations between a Lo register and an 8-bit immediate value. The THUMB assembler syntax is shown in Table 4-4. NOTE All instructions in this group set the CPSR condition codes.
Table 4-4. Summary of Format 3 Instructions OP 00 01 THUMB Assembler MOV Rd, #Offset8 CMP Rd, #Offset8 ARM Equipment MOVS Rd, #Offset8 CMP Rd, #Offset8 Action Move 8-bit immediate value into Rd. Compare contents of Rd with 8-bit immediate value. Add 8-bit immediate value to contents of Rd and place the result in Rd. Subtract 8-bit immediate value from contents of Rd and place the result in Rd.
10 11
ADD Rd, #Offset8 SUB Rd, #Offset8
ADDS Rd, Rd, #Offset8 SUBS Rd, Rd, #Offset8
4-9
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-4. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES MOV CMP ADD SUB R0, #128 R2, #62 R1, #255 R6, #145 ; ; ; ; R0 := 128 and set condition codes Set condition codes on R2 - 62 R1 := R1 + 255 and set condition codes R6 := R6 - 145 and set condition codes
4-10
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
FORMAT 4: ALU OPERATIONS
15 0
14 0
13 0
12 0
11 0
10 0
9 Op
6
5 Rs
3
2 Rd
0
[2:0] Source/Destination Register [5:3] Source Register 2 [9:6] Opcode
Figure 4-5. Format 4 OPERATION The following instructions perform ALU operations on a Lo register pair. NOTE All instructions in this group set the CPSR condition codes.
Table 4-5. Summary of Format 4 Instructions OP 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 THUMB Assembler AND Rd, Rs EOR Rd, Rs LSL Rd, Rs LSR Rd, Rs ASR Rd, Rs ADC Rd, Rs SBC Rd, Rs ROR Rd, Rs TST Rd, Rs NEG Rd, Rs CMP Rd, Rs CMN Rd, Rs ORR Rd, Rs MUL Rd, Rs BIC Rd, Rs MVN Rd, Rs ARM Equipment ANDS Rd, Rd, Rs EORS Rd, Rd, Rs MOVS Rd, Rd, LSL Rs MOVS Rd, Rd, LSR Rs MOVS Rd, Rd, ASR Rs ADCS Rd, Rd, Rs SBCS Rd, Rd, Rs MOVS Rd, Rd, ROR Rs TST Rd, Rs RSBS Rd, Rs, #0 CMP Rd, Rs CMN Rd, Rs ORRS Rd, Rd, Rs MULS Rd, Rs, Rd BICS Rd, Rd, Rs MVNS Rd, Rs Action Rd:= Rd AND Rs Rd:= Rd EOR Rs Rd := Rd << Rs Rd := Rd >> Rs Rd := Rd ASR Rs Rd := Rd + Rs + C-bit Rd := Rd - Rs - NOT C-bit Rd := Rd ROR Rs Set condition codes on Rd AND Rs Rd = - Rs Set condition codes on Rd - Rs Set condition codes on Rd + Rs Rd := Rd OR Rs Rd := Rs * Rd Rd := Rd AND NOT Rs Rd := NOT Rs
4-11
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-5. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES EOR ROR NEG CMP MUL R3, R4 R1, R0 R5, R3 R2, R6 R0, R7 ; ; ; ; ; ; ; R3 := R3 EOR R4 and set condition codes Rotate Right R1 by the value in R0, store the result in R1 and set condition codes Subtract the contents of R3 from zero, Store the result in R5. Set condition codes ie R5 = - R3 Set the condition codes on the result of R2 - R6 R0 := R7 * R0 and set condition codes
4-12
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE
15 0
14 0
13 0
12 0
11 0
10 0
9 Op
8
7 H1
6 H2
5 Rs/Hs
3
2 Rd/Hd
0
[2:0] Destination Register [5:3] Source Register [6] Hi Operand Flag 2 [7] Hi Operand Flag 1 [9:8] Opcode
Figure 4-6. Format 5 OPERATION There are four sets of instructions in this group. The first three allow ADD, CMP and MOV operations to be performed between Lo and Hi registers, or a pair of Hi registers. The fourth, BX, allows a Branch to be performed which may also be used to switch processor state. The THUMB assembler syntax is shown in Table 4-6. NOTE In this group only CMP (Op = 01) sets the CPSR condition codes. The action of H1= 0, H2 = 0 for Op = 00 (ADD), Op =01 (CMP) and Op = 10 (MOV) is undefined, and should not be used. Table 4-6. Summary of Format 5 Instructions Op 00 00 00 01 H1 0 1 1 0 H2 1 0 1 1 THUMB assembler ADD Rd, Hs ADD Hd, Rs ADD Hd, Hs CMP Rd, Hs ARM equivalent ADD Rd, Rd, Hs ADD Hd, Hd, Rs ADD Hd, Hd, Hs CMP Rd, Hs Action Add a register in the range 8-15 to a register in the range 0-7. Add a register in the range 0-7 to a register in the range 8-15. Add two registers in the range 8-15 Compare a register in the range 0-7 with a register in the range 8-15. Set the condition code flags on the result. Compare a register in the range 8-15 with a register in the range 0-7. Set the condition code flags on the result.
01
1
0
CMP Hd, Rs
CMP Hd, Rs
4-13
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
Table 4-6. Summary of Format 5 Instructions (Continued) Op 01 H1 1 H2 1 THUMB assembler CMP Hd, Hs ARM equivalent CMP Hd, Hs Action Compare two registers in the range 8-15. Set the condition code flags on the result. Move a value from a register in the range 8-15 to a register in the range 07. Move a value from a register in the range 0-7 to a register in the range 8-15. Move a value between two registers in the range 8-15. Perform branch (plus optional state change) to address in a register in the range 0-7. Perform branch (plus optional state change) to address in a register in the range 8-15.
10
0
1
MOV Rd, Hs
MOV Rd, Hs
10
1
0
MOV Hd, Rs
MOV Hd, Rs
10 11
1 0
1 0
MOV Hd, Hs BX Rs
MOV Hd, Hs BX Rs
11
0
1
BX Hs
BX Hs
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-6. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. THE BX INSTRUCTION BX performs a Branch to a routine whose start address is specified in a Lo or Hi register. Bit 0 of the address determines the processor state on entry to the routine: Bit 0 = 0 Bit 0 = 1 Causes the processor to enter ARM state. Causes the processor to enter THUMB state. NOTE The action of H1 = 1 for this instruction is undefined, and should not be used.
4-14
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
EXAMPLES Hi-Register Operations ADD CMP MOV PC, R5 R4, R12 R15, R14 ; ; ; ; ; PC := PC + R5 but don't set the condition codes. Set the condition codes on the result of R4 - R12. Move R14 (LR) into R15 (PC) but don't set the condition codes, eg. return from subroutine.
Branch and Exchange ; Switch from THUMB to ARM state. ; Load address of outofTHUMB into R1. ; Transfer the contents of R11 into the PC. ; Bit 0 of R11 determines whether ; ARM or THUMB state is entered, ie. ARM state here.
ADR MOV BX
R1,outofTHUMB R11,R1 R11
* *
ALIGN CODE32 outofTHUMB
; Now processing ARM instructions...
USING R15 AS AN OPERAND If R15 is used as an operand, the value will be the address of the instruction + 4 with bit 0 cleared. Executing a BX PC in THUMB state from a non-word aligned address will result in unpredictable execution.
4-15
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
FORMAT 6: PC-RELATIVE LOAD
15 0
14 0
13 0
12 0
11 0
10 Rd
8
7 Word 8
0
[7:0] Immediate Value [10:8] Destination Register
Figure 4-7. Format 6
OPERATION This instruction loads a word from an address specified as a 10-bit immediate offset from the PC. The THUMB assembler syntax is shown below. Table 4-7. Summary of PC-Relative Load Instruction THUMB assembler LDR Rd, [PC, #Imm] ARM equivalent LDR Rd, [R15, #Imm] Action Add unsigned offset (255 words, 1020 bytes) in Imm to the current value of the PC. Load the word from the resulting address into Rd.
NOTE:
The value specified by #Imm is a full 10-bit address, but must always be word-aligned (ie with bits 1:0 set to 0), since the assembler places #Imm >> 2 in field Word 8. The value of the PC will be 4 bytes greater than the address of this instruction, but bit 1 of the PC is forced to 0 to ensure it is word aligned.
4-16
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LDR R3,[PC,#844] ; ; ; ; ; Load into R3 the word found at the address formed by adding 844 to PC. bit[1] of PC is forced to zero. Note that the THUMB opcode will contain 211 as the Word8 value.
4-17
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
FORMAT 7: LOAD/STORE WITH REGISTER OFFSET
15 0
14 1
13 0
12 1
11 L
10 B
9 0
8 Ro
6
5 Rb
3
2 Rd
0
[2:0] Source/Destination Register [5:3] Base Register [8:6] Offset Register [10] Byte/Word Flag
0 = Transfer word quantity 1 = Transfer byte quantity
[11] Load/Store Flag
0 = Store to memory 1 = Load from memory
Figure 4-8. Format 7
4-18
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
OPERATION These instructions transfer byte or word values between registers and memory. Memory addresses are pre-indexed using an offset register in the range 0-7. The THUMB assembler syntax is shown in Table 4-8. Table 4-8. Summary of Format 7 Instructions L 0 B 0 THUMB assembler STR Rd, [Rb, Ro] ARM equivalent STR Rd, [Rb, Ro] Action Pre-indexed word store: Calculate the target address by adding together the value in Rb and the value in Ro. Store the contents of Rd at the address. Pre-indexed byte store: Calculate the target address by adding together the value in Rb and the value in Ro. Store the byte value in Rd at the resulting address. Pre-indexed word load: Calculate the source address by adding together the value in Rb and the value in Ro. Load the contents of the address into Rd. Pre-indexed byte load: Calculate the source address by adding together the value in Rb and the value in Ro. Load the byte value at the resulting address.
0
1
STRB Rd, [Rb, Ro]
STRB Rd, [Rb, Ro]
1
0
LDR Rd, [Rb, Ro]
LDR Rd, [Rb, Ro]
1
1
LDRB Rd, [Rb, Ro]
LDRB Rd, [Rb, Ro]
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-8. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STR LDRB R3, [R2,R6] R2, [R0,R7] ; ; ; ; Store word in R3 at the address formed by adding R6 to R2. Load into R2 the byte found at the address formed by adding R7 to R0.
4-19
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
FORMAT 8: LOAD/STORE SIGN-EXTENDED BYTE/HALFWORD
15 0
14 1
13 0
12 1
11 H
10 S
9 1
8 Ro
6
5 Rb
3
2 Rd
0
[2:0] Destination Register [5:3] Base Register [8:6] Offset Register [10] Sign-Extended Flag
0 = Operand not sing-extended 1 = Operand sing-extended
[11] H Flag
Figure 4-9. Format 8 OPERATION These instructions load optionally sign-extended bytes or halfwords, and store halfwords. The THUMB assembler syntax is shown below. Table 4-9. Summary of format 8 instructions L 0 B 0 THUMB assembler STRH Rd, [Rb, Ro] ARM equivalent STRH Rd, [Rb, Ro] Store halfword: Add Ro to base address in Rb. Store bits 0-15 of Rd at the resulting address. 0 1 LDRH Rd, [Rb, Ro] LDRH Rd, [Rb, Ro] Load halfword: Add Ro to base address in Rb. Load bits 0-15 of Rd from the resulting address, and set bits 16-31 of Rd to 0. 1 0 LDSB Rd, [Rb, Ro] LDRSB Rd, [Rb, Ro] Load sign-extended byte: Add Ro to base address in Rb. Load bits 0-7 of Rd from the resulting address, and set bits 8-31 of Rd to bit 7. 1 1 LDSH Rd, [Rb, Ro] LDRSH Rd, [Rb, Ro] Load sign-extended halfword: Add Ro to base address in Rb. Load bits 0-15 of Rd from the resulting address, and set bits 16-31 of Rd to bit 15. Action
4-20
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-9. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STRH LDSB LDSH R4, [R3, R0] R2, [R7, R1] R3, [R4, R2] ; ; ; ; ; ; Store the lower 16 bits of R4 at the address formed by adding R0 to R3. Load into R2 the sign extended byte found at the address formed by adding R1 to R7. Load into R3 the sign extended halfword found at the address formed by adding R2 to R4.
4-21
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
FORMAT 9: LOAD/STORE WITH IMMEDIATE OFFSET
15 0
14 1
13 1
12 B
11 L
10 Offset5
6
5 Rb
3
2 Rd
0
[2:0] Source/Destination Register [5:3] Base Register [10:6] Offset Register [11] Load/Store Flag
0 = Store to memory 1 = Load from memory
[12] Byte/Word Flad
0 = Transfer word quantity 1 = Transfer byte quantity
Figure 4-10. Format 9
4-22
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7-bit offset. The THUMB assembler syntax is shown in Table 4-10. Table 4-10. Summary of Format 9 Instructions L 0 B 0 THUMB assembler STR Rd, [Rb, #Imm] ARM equivalent STR Rd, [Rb, #Imm] Action Calculate the target address by adding together the value in Rb and Imm. Store the contents of Rd at the address. Calculate the source address by adding together the value in Rb and Imm. Load Rd from the address. Calculate the target address by adding together the value in Rb and Imm. Store the byte value in Rd at the address. Calculate source address by adding together the value in Rb and Imm. Load the byte value at the address into Rd.
1
0
LDR Rd, [Rb, #Imm]
LDR Rd, [Rb, #Imm]
0
1
STRB Rd, [Rb, #Imm]
STRB Rd, [Rb, #Imm]
1
1
LDRB Rd, [Rb, #Imm]
LDRB Rd, [Rb, #Imm]
NOTE:
For word accesses (B = 0), the value specified by #Imm is a full 7-bit address, but mus t be word-aligned (ie with bits 1:0 set to 0), since the assembler places #Imm >> 2 in the Offset5 field.
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-10. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LDR R2, [R5,#116] ; ; ; ; ; ; ; ; Load into R2 the word found at the address formed by adding 116 to R5. Note that the THUMB opcode will contain 29 as the Offset5 value. Store the lower 8 bits of R1 at the address formed by adding 13 to R0. Note that the THUMB opcode will contain 13 as the Offset5 value.
STRB
R1, [R0,#13]
4-23
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
FORMAT 10: LOAD/STORE HALFWORD
15 0
14 1
13 0
12 0
11 L
10 Offset5
6
5 Rb
3
2 Rd
0
[2:0] Source/Destination Register [5:3] Base Register [10:6] Immediate Value [11] Load/Store Flag
0 = Store to memory 1 = Load from memory
Figure 4-11. Format 10
OPERATION These instructions transfer halfword values between a Lo register and memory. Addresses are pre-indexed, using a 6-bit immediate value. The THUMB assembler syntax is shown in Table 4-11. Table 4-11. Halfword Data Transfer Instructions L 0 1 THUMB assembler STRH Rd, [Rb, #Imm] LDRH Rd, [Rb, #Imm] ARM equivalent STRH Rd, [Rb, #Imm] LDRH Rd, [Rb, #Imm] Action Add #Imm to base address in Rb and store bits 0 - 15 of Rd at the resulting address. Add #Imm to base address in Rb. Load bits 0-15 from the resulting address into Rd and set bits 16-31 to zero.
NOTE:
#Imm is a full 6-bit address but must be halfword-aligned (ie with bit 0 set to 0) since the assembler places #Imm >> 1 in the Offset5 field.
4-24
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-11. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STRH R6, [R1, #56] ; ; ; ; ; ; Store the lower 16 bits of R4 at the address formed by adding 56 R1. Note that the THUMB opcode will contain 28 as the Offset5 value. Load into R4 the halfword found at the address formed by adding 4 to R7. Note that the THUMB opcode will contain 2 as the Offset5 value.
LDRH
R4, [R7, #4]
4-25
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
FORMAT 11: SP-RELATIVE LOAD/STORE
15 1
14 0
13 0
12 1
11 L
10 Rd
8
7 Word 8
0
[7:0] Immediate Value [10:8] Destination Register [11] Load/Store Bit
0 = Store to memory 1 = Load from memory
Figure 4-12. Format 11 OPERATION The instructions in this group perform an SP-relative load or store. The THUMB assembler syntax is shown in the following table. Table 4-12. SP-Relative Load/Store Instructions L 0 THUMB assembler STR Rd, [SP, #Imm] ARM equivalent STR Rd, [R13 #Imm] Action Add unsigned offset (255 words, 1020 bytes) in Imm to the current value of the SP (R7). Store the contents of Rd at the resulting address. Add unsigned offset (255 words, 1020 bytes) in Imm to the current value of the SP (R7). Load the word from the resulting address into Rd.
1
LDR Rd, [SP, #Imm]
LDR Rd, [R13 #Imm]
NOTE:
The offset supplied in #Imm is a full 10-bit address, but must always be word-aligned (ie bits 1:0 set to 0), since the assembler places #Imm >> 2 in the Word8 field.
4-26
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-12. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STR R4, [SP,#492] ; ; ; ; Store the contents of R4 at the address formed by adding 492 to SP (R13). Note that the THUMB opcode will contain 123 as the Word8 value.
4-27
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
FORMAT 12: LOAD ADDRESS
15 1
14 0
13 1
12 0
11 SP
10 Rd
8
7 Word 8
0
[7:0] 8-bit Unsigned Constant [10:8] Destination Register [11] Source
0 = PC 1 = SP
Figure 4-13. Format 12 OPERATION These instructions calculate an address by adding an 10-bit constant to either the PC or the SP, and load the resulting address into a register. The THUMB assembler syntax is shown in the following table. Table 4-13. Load Address L 0 1
NOTE:
THUMB assembler ADD Rd, PC, #Imm ADD Rd, SP, #Imm
ARM equivalent ADD Rd, R15, #Imm ADD Rd, R13, #Imm
Action Add #Imm to the current value of the program counter (PC) and load the result into Rd. Add #Imm to the current value of the stack pointer (SP) and load the result into Rd.
The value specified by #Imm is a full 10-bit value, but this must be word-aligned (ie with bits 1:0 set to 0) since the assembler places #Imm >> 2 in field Word 8.
Where the PC is used as the source register (SP = 0), bit 1 of the PC is always read as 0. The value of the PC will be 4 bytes greater than the address of the instruction before bit 1 is forced to 0. The CPSR condition codes are unaffected by these instructions.
4-28
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-13. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD R2, PC, #572 ; ; ; ; ; ; ; ; R2 := PC + 572, but don't set the condition codes. bit[1] of PC is forced to zero. Note that the THUMB opcode will contain 143 as the Word8 value. R6 := SP (R13) + 212, but don't set the condition codes. Note that the THUMB opcode will contain 53 as the Word 8 value.
ADD
R6, SP, #212
4-29
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
FORMAT 13: ADD OFFSET TO STACK POINTER
15 1
14 0
13 1
12 1
11 0
10 0
9 0
8 0
7 S
6 SWord 7
0
[6:0] 7-bit Immediate Value [7] Sign Flag
0 = Offset is positive 1 = Offset is negative
Figure 4-14. Format 13 OPERATION This instruction adds a 9-bit signed constant to the stack pointer. The following table shows the THUMB assembler syntax. Table 4-14. The ADD SP Instruction L 0 1
NOTE:
THUMB assembler ADD SP, #Imm ADD SP, # -Imm
ARM equivalent ADD R13, R13, #Imm SUB R13, R13, #Imm
Action Add #Imm to the stack pointer (SP). Add #-Imm to the stack pointer (SP).
The offset specified by #Imm can be up to -/+ 508, but must be word-aligned (ie with bits 1:0 set to 0) since the assembler converts #Imm to an 8-bit sign + magnitude number before placing it in field SWord7. The condition codes are not set by this instruction.
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-14. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD SP, #268 ; ; ; ; ; ; SP (R13) := SP + 268, but don't set the condition codes. Note that the THUMB opcode will contain 67 as the Word7 value and S=0. SP (R13) := SP - 104, but don't set the condition codes. Note that the THUMB opcode will contain 26 as the Word7 value and S=1.
ADD
SP, #-104
4-30
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
FORMAT 14: PUSH/POP REGISTERS
15 1
14 0
13 1
12 1
11 L
10 1
9 0
8 R
7 Rlist
0
[7:0] Register List [8] PC/LR Bit
0 = Do not store LR/Load PC 1 = Store LR/Load PC
[11] Load/Store Bit
0 = Store to memory 1 = Load from memory
Figure 4-15. Format 14 OPERATION The instructions in this group allow registers 0-7 and optionally LR to be pushed onto the stack, and registers 0-7 and optionally PC to be popped off the stack. The THUMB assembler syntax is shown in Table 4-15. NOTE The stack is always assumed to be Full Descending.
Table 4-15. PUSH and POP Instructions L 0 0 B 0 1 THUMB assembler PUSH { Rlist } PUSH { Rlist, LR } ARM equivalent STMDB R13!, { Rlist } STMDB R13!, { Rlist, R14 } LDMIA R13!, { Rlist } Action Push the registers specified by Rlist onto the stack. Update the stack pointer. Push the Link Register and the registers specified by Rlist (if any) onto the stack. Update the stack pointer. Pop values off the stack into the registers specified by Rlist. Update the stack pointer. Pop values off the stack and load into the registers specified by Rlist. Pop the PC off the stack. Update the stack pointer.
1
0
POP { Rlist }
1
1
POP { Rlist, PC }
LDMIA R13!, {Rlist, R15}
4-31
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-15. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES PUSH {R0-R4,LR} ; ; ; ; ; ; ; Store R0,R1,R2,R3,R4 and R14 (LR) at the stack pointed to by R13 (SP) and update R13. Useful at start of a sub-routine to save workspace and return address. Load R2,R6 and R15 (PC) from the stack pointed to by R13 (SP) and update R13. Useful to restore workspace and return from sub-routine.
POP
{R2,R6,PC}
4-32
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
FORMAT 15: MULTIPLE LOAD/STORE
15 1
14 1
13 0
12 0
11 L
10 RB
8
7 Rlist
0
[7:0] Register List [10:8] Base Register [11] Load/Store Bit
0 = Store to memory 1 = Load from memory
Figure 4-16. Format 15 OPERATION These instructions allow multiple loading and storing of Lo registers. The THUMB assembler syntax is shown in the following table. Table 4-16. The Multiple Load/Store Instructions L 0 THUMB assembler STMIA Rb!, { Rlist } ARM equivalent STMIA Rb!, { Rlist } Action Store the registers specified by Rlist, starting at the base address in Rb. Write back the new base address. Load the registers specified by Rlist, starting at the base address in Rb. Write back the new base address.
1
LDMIA Rb!, { Rlist }
LDMIA Rb!, { Rlist }
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-16. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STMIA R0!, {R3-R7} ; ; ; ; Store the contents of registers R3-R7 starting at the address specified in R0, incrementing the addresses for each word. Write back the updated value of R0.
4-33
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
FORMAT 16: CONDITIONAL BRANCH
15 1
14 1
13 0
12 1
11 Cond
8
7 SOffset 8
0
[7:0] 8-bit Signed Immediate [11:8] Condition
Figure 4-17. Format 16 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction. The THUMB assembler syntax is shown in the following table. Table 4-17. The Conditional Branch Instructions L 0000 0001 0010 0011 0100 0101 0110 0111 1000 THUMB assembler BEQ label BNE label BCS label BCC label BMI label BPL label BVS label BVC label BHI label ARM equivalent BEQ label BNE label BCS label BCC label BMI label BPL label BVS label BVC label BHI label Action Branch if Z set (equal) Branch if Z clear (not equal) Branch if C set (unsigned higher or same) Branch if C clear (unsigned lower) Branch if N set (negative) Branch if N clear (positive or zero) Branch if V set (overflow) Branch if V clear (no overflow) Branch if C set and Z clear (unsigned higher)
4-34
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
Table 4-17. The Conditional Branch Instructions (Continued) L 1001 1010 1011 1100 1101 THUMB assembler BLS label BGE label BLT label BGT label BLE label ARM equivalent BLS label BGE label BLT label BGT label BLE label Action Branch if C clear or Z set (unsigned lower or same) Branch if N set and V set, or N clear and V clear (greater or equal) Branch if N set and V clear, or N clear and V set (less than) Branch if Z clear, and either N set and V set or N clear and V clear (greater than) Branch if Z set, or N set and V clear, or N clear and V set (less than or equal)
NOTES 1. While label specifies a full 9-bit two's complement address, this must always be halfword-aligned (ie with bit 0 set to 0) since the assembler actually places label >> 1 in field SOffset8. 2. Cond = 1110 is undefined, and should not be used. Cond = 1111 creates the SWI instruction: see .
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-1. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES CMP R0, #45 ; BGT over
* * *
Branch to over-if R0 > 45. ; Note that the THUMB opcode will contain ; the number of halfwords to offset. ; Must be halfword aligned.
over
4-35
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
FORMAT 17: SOFTWARE INTERRUPT
15 1
14 1
13 0
12 1
11 1
10 1
9 1
8 1
7 Value 8
0
[7:0] Comment Field
Figure 4-18. Format 17 OPERATION The SWI instruction performs a software interrupt. On taking the SWI, the processor switches into ARM state and enters Supervisor (SVC) mode. The THUMB assembler syntax for this instruction is shown below. Table 4-18. The SWI Instruction THUMB assembler SWI Value 8 ARM equivalent SWI Value 8 Action Perform Software Interrupt: Move the address of the next instruction into LR, move CPSR to SPSR, load the SWI vector address (0x8) into the PC. Switch to ARM state and enter SVC mode.
NOTE:
Value8 is used solely by the SWI handler; it is ignored by the processor.
INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-18. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES SWI 18 ; Take the software interrupt exception. ; Enter Supervisor mode with 18 as the ; requested SWI number.
4-36
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
FORMAT 18: UNCONDITIONAL BRANCH
15 1
14 1
13 1
12 0
11 0
10 Offset11
0
[10:0] Immediate Value
Figure 4-19. Format 18 OPERATION This instruction performs a PC-relative Branch. The THUMB assembler syntax is shown below. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction. Table 4-19. Summary of Branch Instruction THUMB assembler B label
NOTE:
ARM equivalent BAL label (halfword offset)
Action Branch PC relative +/- Offset11 << 1, where label is PC +/- 2048 bytes.
The address specified by label is a full 12-bit two's complement address, but must always be halfword aligned (ie bit 0 set to 0), since the assembler places label >> 1 in the Offset11 field.
EXAMPLES here B here B jimmy
* * * *
; ; ; ;
Branch onto itself. Assembles to 0xE7FE. (Note effect of PC offset). Branch to 'jimmy'. Note that the THUMB opcode will contain the number of
jimmy
; halfwords to offset. ; Must be halfword aligned.
4-37
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
FORMAT 19: LONG BRANCH WITH LINK
15 1
14 1
13 1
12 1
11 H
10 Offset
0
[10:0] Long Branch and Link Offset High/Low [11] Low/High Offset Bit
0 = Offset high 1 = Offset low
Figure 4-20. Format 19 OPERATION This format specifies a long branch with link. The assembler splits the 23-bit two's complement half-word offset specified by the label into two 11-bit halves, ignoring bit 0 (which must be 0), and creates two THUMB instructions. Instruction 1 (H = 0) In the first instruction the Offset field contains the upper 11 bits of the target address. This is shifted left by 12 bits and added to the current PC address. The resulting address is placed in LR. Instruction 2 (H =1) In the second instruction the Offset field contains an 11-bit representation lower half of the target address. This is shifted left by 1 bit and added to LR. LR, which now contains the full 23-bit address, is placed in PC, the address of the instruction following the BL is placed in LR and bit 0 of LR is set. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction
4-38
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
INSTRUCTION CYCLE TIMES
This instruction format does not have an equivalent ARM instruction. Table 4-20. The BL Instruction L 0 1 THUMB assembler BL label none ARM equivalent Action LR := PC + OffsetHigh << 12 temp := next instruction address PC := LR + OffsetLow << 1 LR := temp | 1 EXAMPLES BL faraway next
* *
faraway
* *
; ; ; ; ; ; ;
Unconditionally Branch to 'faraway' and place following instruction address, ie "next", in R14,the Link register and set bit 0 of LR high. Note that the THUMB opcodes will contain the number of halfwords to offset. Must be Half-word aligned.
4-39
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
INSTRUCTION SET EXAMPLES
The following examples show ways in which the THUMB instructions may be used to generate small and efficient code. Each example also shows the ARM equivalent so these may be compared. MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following shows code to multiply by various constants using 1, 2 or 3 Thumb instructions alongside the ARM equivalents. For other constants it is generally better to use the built-in MUL instruction rather than using a sequence of 4 or more instructions. Thumb ARM
1. Multiplication by 2^n (1,2,4,8,...) LSL Ra, Rb, LSL #n ; MOV Ra, Rb, LSL #n
2. Multiplication by 2^n+1 (3,5,9,17,...) LSL ADD Rt, Rb, #n Ra, Rt, Rb ; ADD Ra, Rb, Rb, LSL #n
3. Multiplication by 2^n-1 (3,7,15,...) LSL SUB Rt, Rb, #n Ra, Rt, Rb ; RSB Ra, Rb, Rb, LSL #n
4. Multiplication by -2^n (-2, -4, -8, ...) LSL MVN Ra, Rb, #n Ra, Ra ; MOV Ra, Rb, LSL #n ; RSB Ra, Ra, #0
5. Multiplication by -2^n-1 (-3, -7, -15, ...) LSL SUB Rt, Rb, #n Ra, Rb, Rt ; SUB Ra, Rb, Rb, LSL #n
Multiplication by any C = {2^n+1, 2^n-1, -2^n or -2^n-1} * 2^n Effectively this is any of the multiplications in 2 to 5 followed by a final shift. This allows the following additional constants to be multiplied. 6, 10, 12, 14, 18, 20, 24, 28, 30, 34, 36, 40, 48, 56, 60, 62 ..... (2..5) LSL ; (2..5) ; MOV Ra, Ra, LSL #n
Ra, Ra, #n
4-40
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code. Thumb code ;signed_divide ; Signed divide of R1 by R0: returns quotient in R0, ; remainder in R1
;Get abs value of R0 into R3 ASR R2, R0, #31 EOR R0, R2 SUB R3, R0, R2
; Get 0 or -1 in R2 depending on sign of R0 ; EOR with -1 (0xFFFFFFFF) if negative ; and ADD 1 (SUB -1) to get abs value
;SUB always sets flag so go & report division by 0 if necessary BEQ divide_by_zero ;Get abs value of R1 by xoring with 0xFFFFFFFF and adding 1 if negative ASR R0, R1, #31 ; Get 0 or -1 in R3 depending on sign of R1 EOR R1, R0 ; EOR with -1 (0xFFFFFFFF) if negative SUB R1, R0 ; and ADD 1 (SUB -1) to get abs value ;Save signs (0 or -1 in R0 & R2) for later use in determining ; sign of quotient & remainder. PUSH {R0, R2} ;Justification, shift 1 bit at a time until divisor (R0 value) ; is just <= than dividend (R1 value). To do this shift dividend ; right by 1 and stop as soon as shifted value becomes >. LSR R0, R1, #1 MOV R2, R3 B %FT0 just_l LSL R2, #1 0 CMP R2, R0 BLS just_l MOV R0, #0 ; Set accumulator to 0 B %FT0 ; Branch into division loop div_l 0 LSR CMP BCC SUB ADC CMP BNE R2, #1 R1, R2 %FT0 R1, R2 R0, R0 R2, R3 div_l
; Test subtract ; If successful do a real subtract ; Shift result and add 1 if subtract succeeded ; Terminate when R2 == R3 (ie we have just ; tested subtracting the 'ones' value).
0
4-41
THUMB INSTRUCTION SET
S3C2400X01 RISC MICROPROCESSOR
Now fix up the signs of the quotient (R0) and remainder (R1) POP {R2, R3} ; Get dividend/divisor signs back EOR R3, R2 ; Result sign EOR R0, R3 ; Negate if result sign = - 1 SUB R0, R3 EOR R1, R2 ; Negate remainder if dividend sign = - 1 SUB R1, R2 MOV pc, lr ARM Code signed_divide ANDS RSBMI EORS ;ip bit 31 = sign of result ;ip bit 30 = sign of a2 RSBCS ; a4, a1, #&80000000 a1, a1, #0 ip, a4, a2, ASR #32 Effectively zero a4 as top bit will be shifted out later
a2, a2, #0
;Central part is identical code to udiv (without MOV a4, #0 which comes for free as part of signed entry sequence) MOVS a3, a1 BEQ divide_by_zero just_l CMP MOVLS BLO div_l CMP ADC SUBCS TEQ MOVNE BNE MOV MOVS RSBCS RSBMI MOV a2, a3 a4, a4, a4 a2, a2, a3 a3, a1 a3, a3, LSR #1 s_loop2 a1, a4 ip, ip, ASL #1 a1, a1, #0 a2, a2, #0 pc, lr a3, a2, LSR #1 a3, a3, LSL #1 s_loop ; Justification stage shifts 1 bit at a time ; NB: LSL #1 is always OK if LS succeeds
4-42
S3C2400X01 RISC MICROPROCESSOR
THUMB INSTRUCTION SET
DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code. Thumb Code udiv10 MOV LSR SUB LSR ADD LSR ADD LSR ADD LSR ASL ADD ASL SUB CMP BLT ADD SUB 0 MOV ARM Code udiv10 SUB SUB ADD ADD ADD MOV ADD SUBS ADDPL ADDMI MOV a2, a1, #10 a1, a1, a1, lsr #2 a1, a1, a1, lsr #4 a1, a1, a1, lsr #8 a1, a1, a1, lsr #16 a1, a1, lsr #3 a3, a1, a1, asl #2 a2, a2, a3, asl #1 a1, a1, #1 a2, a2, #10 pc, lr ; Take argument in a1 returns quotient in a1, ; remainder in a2 pc, lr a2, a1 a3, a1, #2 a1, a3 a3, a1, #4 a1, a3 a3, a1, #8 a1, a3 a3, a1, #16 a1, a3 a1, #3 a3, a1, #2 a3, a1 a3, #1 a2, a3 a2, #10 %FT0 a1, #1 a2, #10 ; Take argument in a1 returns quotient in a1, ; remainder in a2
4-43
S3C2400 RISC MICROPROCESSOR
MEMORY CONTROLLER
5
MEMORY CONTROLLER
OVERVIEW
The S3C2400 memory controller provides the necessary memory control signals for external memory access. S3C2400 has the following features; -- Little/Big endian (selectable by a S/W) -- Address space: 32Mbytes per each bank (total 256MB: 8 banks) -- Programmable access size (8/16/32-bit) for all banks -- Total 8 memory banks 6 memory banks for ROM, SRAM etc. 2 memory banks for ROM, SRAM, EDO/SDRAM etc . -- 7 fixed memory bank start address and programmble bank size -- 1 flexible memory bank start address and programmable bank size -- Programmable access cycles for all memory banks -- External wait to extend the bus cycles -- Supports self-refresh mode in DRAM/SDRAM for power-down -- Supports asymmetrically or symmetrically addressable DRAM
5-1
MEMORY CONTROLLER
S3C2400 RISC MICROPROCESSOR
0x1000_0000 0x0E00_0000 0x0C00_0000 0x0A00_0000 0x0800_0000 0x0600_0000 0x0400_0000 0x0200_0000 0x0000_0000
SROM/DRAM/SDRAM (nGCS7) SROM/DRAM/SDRAM (nGCS6) SROM (nGCS5) SROM (nGCS4) SROM (nGCS3) SROM (nGCS2) SROM (nGCS1) SROM (nGCS0)
2MB/4MB/8MB/ 16MB/32MB 2MB/4MB/8MB/ 16MB/32MB 32MB 32MB 32MB 32MB
Refer to Table 4-1
256MB SA[27:0] Accessable Region
0x15FF_FFFF 32MB 0x1500_0000 32MB 0x1400_0000
Special Function Register (APB) Special Function Register (AHB)
NOTE:
SROM means ROM or SRAM type memory
Figure 5-1. S3C2400 Memory Map after Reset
Table 5-1. Bank 6/7 Address Address Bank 6 Start address End address Bank 7 Start address End address
NOTE:
2MB
4MB
8MB
16MB
32MB
0xc00_0000 0xc1f_ffff
0xc00_0000 0xc3f_ffff
0xc00_0000 0xc7f_ffff
0xc00_0000 0xcff_ffff
0xc00_0000 0xdff_ffff
0xc20_0000 0xc3f_ffff
0xc40_0000 0xc7f_ffff
0xc80_0000 0xcff_ffff
0xd00_0000 0xdff_ffff
0xe00_0000 0xfff_ffff
Bank 6 and 7 must have the same memory size.
5-2
S3C2400 RISC MICROPROCESSOR
MEMORY CONTROLLER
FUNCTION DESCRIPTION
BANK0 BUS WIDTH The data bus width of BANK0 (nGCS0) should be configured as one of 8-bit,16-bit and 32-bit. Because the BANK0 is the booting ROM bank(map to 0x0000_0000), the bus width of BANK0 should be determined before the first ROM access, which will be determined by the logic level of OM[1:0] at Reset. OM1 (Operating Mode 1) 0 0 1 1 Programming Memory Controller All thirteen memory control registers have to be written using the STMIA instruction as shown in the following example; ;Set memory control registers ldr r0,=SMRDATA ldr r1,=BWSCON add r2, r0, #52 0 ldr r3, [r0], #4 str r3, [r1], #4 cmp r2, r0 bne %B0 DATA DCD 0x22221210 DCD 0x00000600 DCD 0x00000700 DCD 0x00000700 DCD 0x00000700 DCD 0x00000700 DCD 0x00000700 DCD 0x0001002a DCD 0x0001002a DCD 0x00960000 + 953 DCD 0x0 DCD 0x20 DCD 0x20 OM0 (Operating Mode 0) 0 1 0 1 Booting ROM Data width 8-bit 16-bit 32-bit Test Mode
; BWSCON Address ; End address of SMRDATA
SMRDATA
; ; ; ; ; ; ; ; ; ; ; ; ;
BWSCON GCS0 GCS1 GCS2 GCS3 GCS4 GCS5 GCS6, EDO DRAM(Trcd=3, Tcas=2, Tcp=1, CAN=10bit) GCS7, EDO DRAM Refresh(REFEN=1, TREFMD=0, Trp=3, Trc=5, Tchr=3) Bank Size, 32MB/32MB MRSR 6(CL=2) MRSR 7(CL=2)
MEMORY (SROM/DRAM/SDRAM) ADDRESS PIN CONNECTIONS Memory Address Pin A0 A1
***
S3C2400 Address
@ 8-bit Data Bus
S3C2400 Address
@ 16-bit Data Bus
S3C2400 Address
@ 32-bit Data Bus
A0 A1
***
A1 A2
***
A2 A3
***
5-3
MEMORY CONTROLLER
S3C2400 RISC MICROPROCESSOR
SDRAM BANK ADDRESS PIN CONNECTION Table 5-2. SDRAM Bank Address configuration Bank Size 2MByte Bus Width x8 x 16 4MB x8 x 16 x 32 8MB x 16 x 32 x8 x8 x 16 x 16 x 32 16MB x 32 x8 x8 x 16 x 16 x 32 x 32 x8 x 16 32MB x 16 x 16 x 32 x 32 x 16 x 32 x8 x 16 256Mb 128Mb 64Mb 128Mb 16Mb 64Mb 64Mb 16Mb 16Mb Base Component 16Mbit Memory Configuration (1M x 8 x 2B) x 1 (512K x 16 x 2B) x 1 (2M x 4 x 2B) x 2 (1M x 8 x 2B) x 2 (512K x 16 x 2B) x 2 (2M x 4 x 2B) x 4 (1M x 8 x 2B) x 4 (4M x 8 x 2B) x 1 (2M x 8 x 4B) x 1 (2M x 16 x 2B) x 1 (1M x 16 x 4B) x 1 (512K x 32 x 4B) x 1 (2M x 4 x 2B) x 8 (8M x 4 x 2B) x 2 (4M x 4 x 4B) x 2 (4M x 8 x 2B) x 2 (2M x 8 x 4B) x 2 (2M x 16 x 2B) x 2 (1M x 16 x 4B) x 2 (4M x 8 x 4B) x 1 (2M x 16 x 4B) x 1 (8M x 4 x 2B) x 4 (4M x 4 x 4B) x 4 (4M x 8 x 2B) x 4 (2M x 8 x 4B) x 4 (4M x 8 x 4B) x 2 (2M x 16 x 4B) x 2 (8M x 8 x 4B) x 1 (4M x 16 x 4B) x 1 A24 A[24:23] A24 A[24:23] A[23:22] A23 A[23:22] A23 A[23:22] A23 A[22:21] A22 A[22:21] A22 A21 Bank Address A20
5-4
S3C2400 RISC MICROPROCESSOR
MEMORY CONTROLLER
nWAIT PIN OPERATION If the WAIT corresponding each memory bank is enabled, the nOE duration should be prolonged by the external nWAIT pin while the memory bank is active. nWAIT is checked from tacc-1. nOE will be deasserted at the next clock after sampling that nWAIT is high. nWE signal have same relation with nOE as 5-14..
HCLK tRC ADDR
nGCS
Tacs Tacc=3 Tcos delayed
nOE
nWAIT
DATA(R)
Figure 5-2. S3C2400 External nWAIT Timing Diagram (Tacc=3)
5-5
MEMORY CONTROLLER
S3C2400 RISC MICROPROCESSOR
nXBREQ/nXBACK Pin Operation If nXBREQ is asserted, S3C2400 will respond by lowering nXBACK. If nXBACK=L, the address/data bus and memory control signals are in Hi-Z state as shown in Table 1-1. When nXBREQ is de-asserted, the nXBACK will be deasserted.
HCLK A[24:0] D[31:0] nGCS nOE nWE nWBE nXBREQ
~ ~ ~ ~
~ ~
nXACK
Figure 5-3. S3C2400 nXBREQ/nXBACK Timing Diagram
~ ~
5-6
S3C2400 RISC MICROPROCESSOR
MEMORY CONTROLLER
ROM Memory Interface Example
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE
D0 D1 D2 D3 D4 D5 D6 D7 nWE nOE nGCSn
Figure 5-4. Memory Interface with 8bit ROM
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE
D0 D1 D2 D3 D4 D5 D6 D7 nWBE0 nOE nGCSn
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE
D8 D9 D10 D11 D12 D13 D14 D15 nWBE1 nOE nGCSn
Figure 5-5. Memory Interface with 8bit ROM x 2
NOTE: When ADDR[n] out of S3C2400 passed through the damping resistances, ADDR[n] are converted into A[n].
5-7
MEMORY CONTROLLER
S3C2400 RISC MICROPROCESSOR
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE
D0 D1 D2 D3 D4 D5 D6 D7
A2 A3 A4 A5 A6 A7 A8 A9 A10 nWBE0 A11 nOE A12 nGCSn A13 A14 A15 A16 A17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE
D8 D9 D10 D11 D12 D13 D14 D15
A2 A3 A4 A5 A6 A7 A8 A9 A10 nWBE1 A11 nOE A12 nGCSn A13 A14 A15 A16 A17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE
A2 A3 A4 A5 A6 A7 A8 A9 A10 nWBE2 A11 nOE A12 nGCSn A13 A14 A15 A16 A17
D16 D17 D18 D19 D20 D21 D22 D23
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE
D24 D25 D26 D27 D28 D29 D30 D31 nWBE3 nOE nGCSn
Figure 5-6. Memory Interface with 8bit ROM x 4
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCE
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nWE nOE nGCSn
Figure 5-7. Memory Interface with 16bit ROM
5-8
S3C2400 RISC MICROPROCESSOR
MEMORY CONTROLLER
SRAM Memory Interface Example
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nUB nLB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nWE nOE nGCSn nBE1 nBE0
Figure 5-8. Memory Interface with 16bit SRAM
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nUB nLB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nWE nOE nGCSn nBE1 nBE0
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nUB nLB
D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 nWE nOE nGCSn nBE2 nBE3
Figure 5-9. Memory Interface with 16bit SRAM x 2
5-9
MEMORY CONTROLLER
S3C2400 RISC MICROPROCESSOR
DRAM Memory Interface Example
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 nRAS0 nCAS0 nCAS1 nWE
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 nRAS nLCAS nUCAS nWE nOE
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Figure 5-10. Memory Interface with 16bit DRAM
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 nRAS0 nCAS0 nCAS1 nWE
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 nRAS nLCAS nUCAS nWE nOE
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 nRAS0 nCAS2 nCAS3 nWE
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 nRAS nLCAS nUCAS nWE nOE
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
Figure 5-11. Memory Interface with 16bit DRAM x 2
5-10
S3C2400 RISC MICROPROCESSOR
MEMORY CONTROLLER
SDRAM Memory Interface Example
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A21 A22 DQM0 DQM1 SCKE SCLK
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nSCS0 nSRAS nSCAS nWE
Figure 5-12. Memory Interface with 16bit SDRAM (4Mx16, 4bank)
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A22 A23 DQM0 DQM1 SCKE SCLK
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nSCS0 nSRAS nSCAS nWE
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A22 A23 DQM2 DQM3 SCKE SCLK
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE
D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 nSCS0 nSRAS nSCAS nWE
Figure 5-13. Memory Interface with 16bit SDRAM (4Mx16 * 2ea, 4bank)
NOTE: Please refer to Table 5-2 the Bank Address configurations of SDRAM.
5-11
MEMORY CONTROLLER
S3C2400 RISC MICROPROCESSOR
PROGRAMMABLE ACCESS CYCLE
HCLK
A[24:0]
nGCS
Tacs Tcos Tacc Tacp Tcoh
Tcah
nOE
nWE
nWBE
D[31:0](R)
D[31:0] (W)
Tacs = 1 cycle Tcos = 1 cycle Tacc = 3 cycles
Tacp = 2 cycles Tcoh = 1 cycle Tcah = 2 cycles
Figure 5-14. S3C2400X nGCS Timing Diagram
5-12
S3C2400 RISC MICROPROCESSOR
MEMORY CONTROLLER
HCLK
ADDR
Row Addr.
Column Addr.
Column Addr.
nRAS
Trp Tcas Tcas Tcp
nCAS
Trcd
nWE/nOE DATA (R) @EDO D[31:0] (W)
Trp = 1 cycle Trcd = 2 cycle
Tcas = 2 cycle Tcp = 2 cycle
Figure 5-15. S3C2400 DRAM Timing Diagram
MCLK
nRAS
~
nCAS
Tcsr
Tchr
~
Tcsr = 1 cycle Tchr = 3 cycle
Figure 5-16. S3C2400 DRAM Refresh Timing Diagram
5-13
MEMORY CONTROLLER
S3C2400 RISC MICROPROCESSOR
MCLK SCKE nSCS Trp
nSRAS
nSCAS
Trcd
ADDR
RA
Ca
Cb
Cc
Cd
Ce
BA
BA
BA
BA
BA
BA
BA
BA
A10/AP
RA
DATA (CL2)
Da
Db
Dc
Dd
De
DATA (CL3)
Da
Db
Dc
Dd
De
nWE
DQM
Bank Precharge
Row Active
Write
Read (CL = 2, CL = 3, BL = 1)
Trp = 2 cycle Trcd = 2 cycle
Tcas = 2 cycle Tcp = 2 cycle
Figure 5-17. S3C2400 SDRAM Timing Diagram
5-14
S3C2400 RISC MICROPROCESSOR
MEMORY CONTROLLER
BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) Register BWSCON Address 0x14000000 R/W R/W Description Bus Width & Wait Status Control Register Reset Value 0x000000
BWSCON ST7
Bit [31]
Description This bit determines SRAM for using UB/LB for bank 7 0 = Not using UB/LB (Pin[154:151] is dedicated nWBE[3:0]) 1 = Using UB/LB (Pin[154:151] is dedicated nBE[3:0]) This bit determines WAIT status for bank 7 0 = WAIT disable 1 = WAIT enable These two bits determine data bus width for bank 7 00 = 8-bit 01 = 16-bit, 10 = 32-bit This bit determines SRAM for using UB/LB for bank 6 0 = Not using UB/LB (Pin[154:151] is dedicated nWBE[3:0]) 1 = Using UB/LB (Pin[154:151] is dedicated nBE[3:0]) This bit determines WAIT status for bank 6 0 = WAIT disable, 1 = WAIT enable These two bits determine data bus width for bank 6 00 = 8-bit 01 = 16-bit, 10 = 32-bit This bit determines SRAM for using UB/LB for bank 5 0 = Not using UB/LB (Pin[154:151] is dedicated nWBE[3:0]) 1 = Using UB/LB (Pin[154:151] is dedicated nBE[3:0]) This bit determines WAIT status for bank 5 0 = WAIT disable, 1 = WAIT enable These two bits determine data bus width for bank 5 00 = 8-bit 01 = 16-bit, 10 = 32-bit This bit determines SRAM for using UB/LB for bank 4 0 = Not using UB/LB (Pin[154:151] is dedicated nWBE[3:0]) 1 = Using UB/LB (Pin[154:151] is dedicated nBE[3:0]) This bit determines WAIT status for bank 4 0 = WAIT disable 1 = WAIT enable These two bits determine data bus width for bank 4 00 = 8-bit 01 = 16-bit, 10 = 32-bit This bit determines SRAM for using UB/LB for bank 3 0 = Not using UB/LB (Pin[154:151] is dedicated nWBE[3:0]) 1 = Using UB/LB (Pin[154:151] is dedicated nBE[3:0]) This bit determines WAIT status for bank 3 0 = WAIT disable 1 = WAIT enable These two bits determine data bus width for bank 3 00 = 8-bit 01 = 16-bit, 10 = 32-bit This bit determines SRAM for using UB/LB for bank 2 0 = Not using UB/LB (Pin[154:151] is dedicated nWBE[3:0]) 1 = Using UB/LB (Pin[154:151] is dedicated nBE[3:0])
Initial state 0
WS7 DW7 ST6
[30] [29:28] [27]
0 0 0
WS6 DW6 ST5
[26] [25:24] [23]
0 0 0
WS5 DW5 ST4
[22] [21:20] [19]
0 0 0
WS4 DW4 ST3
[18] [17:16] [15]
0 0 0
WS3 DW3 ST2
[14] [13:12] [11]
0 0 0
5-15
MEMORY CONTROLLER
S3C2400 RISC MICROPROCESSOR
BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) (Continued) BWSCON WS2 DW2 ST1 Bit [10] [9:8] [7] Description This bit determines WAIT status for bank 2 0 = WAIT disable 1 = WAIT enable These two bits determine data bus width for bank 2 00 = 8-bit 01 = 16-bit, 10 = 32-bit This bit determines SRAM for using UB/LB for bank 1 0 = Not using UB/LB (Pin[154:151] is dedicated nWBE[3:0]) 1 = Using UB/LB (Pin[154:151] is dedicated nBE[3:0]) This bit determines WAIT status for bank 1 0 = WAIT disable, 1 = WAIT enable These two bits determine data bus width for bank 1 00 = 8-bit 01 = 16-bit, 10 = 32-bit Indicates data bus width for bank 0 (read only) 00 = 8-bit 01 = 16-bit, 10 = 32-bit The states are selected by OM[1:0] pins Initial state 0 0 0
WS1 DW1 DW0
[6] [5:4] [2:1]
0 0 -
Reserved
[0]
-
NOTE : 1. All types of master clock in this memory controller correspond to the bus clock. For example, HCLK in DRAM and SRAM is same as the bus clock, and SCLK in SDRAM is also the same as the bus clock. In this chapter (Memory Controller), one clock means one bus clock. 2. nBE[3:0] is the 'AND' signal nWBE[3:0] and nOE
5-16
S3C2400 RISC MICROPROCESSOR
MEMORY CONTROLLER
BANK CONTROL REGISTER (BANKCONn: nGCS0-nGCS5) Register BANKCON0 BANKCON1 BANKCON2 BANKCON3 BANKCON4 BANKCON5 Address 0x14000004 0x14000008 0x1400000C 0x14000010 0x14000014 0x14000018 R/W R/W R/W R/W R/W R/W R/W Description Bank 0 control register Bank 1 control register Bank 2 control register Bank 3 control register Bank 4 control register Bank 5 control register Reset Value 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700
BANKCONn Tacs
Bit [14:13]
Description Address set-up before nGCSn 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Chip selection set-up nOE 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Access cycle 000 = 1 clock 010 = 3 clocks 100 = 6 clocks 110 = 10 clocks 001 011 101 111 = = = = 2 clocks 4 clocks 8 clocks 14 clocks
Initial State 00
Tcos
[12:11]
00
Tacc
[10:8]
111
NOTE: When nWAIT signal is used, Tacc 4 clocks.
Toch
[7:6]
Chip selection hold on nOE 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Address holding time after nGCSn 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Page mode access cycle @ Page mode 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = 6 clocks Page mode configuration 00 = normal (1 data) 01 = 4 data 10 = 8 data 11 = 16 data
000
Tcah
[5:4]
00
Tacp
[3:2]
00
PMC
[1:0]
00
5-17
MEMORY CONTROLLER
S3C2400 RISC MICROPROCESSOR
BANK CONTROL REGISTER (BANKCONn: nGCS6-nGCS7) Register BANKCON6 BANKCON7 Address 0x1400001C 0x14000020 R/W R/W R/W Description Bank 6 control register Bank 7 control register Reset Value 0x18008 0x18008
BANKCONn MT
Bit [16:15]
Description These two bits determine the memory type for bank6 and bank7 00 = ROM or SRAM 01 = Reserved(Don't use) 10 = EDO DRAM 11 = Sync. DRAM
Initial State 11
Memory Type = ROM or SRAM [MT=00] (15-bit) Tacs [14:13] Address set-up before nGCS 00 = 0 clock 01 = 1 clock clocks Chip selection set-up nOE 00 = 0 clock 01 = 1 clock clocks Access cycle 000 = 1 clock 010 = 3 clocks 100 = 6 clocks 110 = 10 clocks 00 10 = 2 clocks 11 = 4 00 10 = 2 clocks 11 = 4 111 001 = 2 clocks 011 = 4 clocks 101 = 8 clocks 111 = 14 clocks 00
Tcos
[12:11]
Tacc
[10:8]
Toch
[7:6]
Chip selection hold on nOE 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Address hold time on nGCSn 00 = 0 clock 01 = 1clock 10 = 2 clocks Page mode access cycle @ Page mode 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = 6 clocks Page mode configuration 00 = normal (1 data) 10 = 8 consecutive accesses 01 = 4 consecutive accesses 11 = 16 consecutive accesses 11 = 4 clocks
Tcah Tacp
[5:4] [3:2]
00 00
PMC
[1:0]
00
Memory Type = EDO DRAM [MT=10] (6-bit) Trcd [5:4] RAS to CAS delay 00 = 1 clock 10 = 3 clocks CAS pulse width 0 = 1 clock CAS pre-charge 0 = 1 clock 00 01 = 2 clocks 11 = 4 clocks 0 1 = 2 clocks 0 1 = 2 clocks 00
Tcas Tcp CAN
[3] [2] [1:0]
Column address number 00 = 8-bit 01 = 9-bit 10 = 10-bit 11 = 11-bit
5-18
S3C2400 RISC MICROPROCESSOR
MEMORY CONTROLLER
BANK CONTROL REGISTER (BANKCONn: nGCS6-nGCS7) (Continued) Memory Type = SDRAM [MT=11] (4-bit) Trcd SCAN [3:2] [1:0] RAS to CAS delay 00 = 2 clocks 01 = 3 clocks Column address number 00 = 8-bit 01 = 9-bit 10 10 = 4 clocks 00 10= 10-bit
SUPPORTED BANK 6/7 MEMORY CONFIGURATION Bank Bank7 Bank6
NOTE:
Support SROM DRAM SROM SDRAM DRAM SROM DRAM DRAM SDRAM SROM SDRAM SDRAM
Not support SDRAM DRAM DRAM SDRAM
SROM means ROM or SRAM type memory
REFRESH CONTROL REGISTER Register REFRESH Address 0x14000024 R/W R/W Description DRAM/SDRAM refresh control register Reset Value 0xac0000
REFRESH REFEN TREFMD
Bit [23] [22]
Description DRAM/SDRAM Refresh Enable 0 = Disable 1 = Enable(self or CBR/auto refresh) DRAM/SDRAM Refresh Mode 0 = CBR/Auto Refresh 1 = Self Refresh In self-refresh time, the DRAM/SDRAM control signals are driven to the appropriate level. DRAM/SDRAM RAS pre-charge Time DRAM: 00 = 1.5 clocks 01 = 2.5 clocks 10 = 3.5 clocks 11 = 4.5 clocks SDRAM: 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = Not support SDRAM RC minimum Time 00 = 4 clocks 01 = 5 clocks 10 = 6 clocks 11 = 7 clocks CAS Hold Time(DRAM) 00 = 1 clock 01 = 2 clocks 10 = 3 clocks 11 = 4 clocks Not use DRAM/SDRAM refresh count value. Please, refer to chap. 6 DRAM refresh controller bus priority section. Refresh period = (211-refresh_count+1)/HCLK Ex) If refresh period is 15.6 us and HCLK is 60 MHz, the refresh count is as follows; refresh count = 211 + 1 - 60x15.6 = 1113
Initial State 1 0
Trp
[21:20]
10
Trc Tchr Reserved Refresh Counter
[19:18] [17:16] [15:11] [10:0]
11 00 0000 0
5-19
MEMORY CONTROLLER
S3C2400 RISC MICROPROCESSOR
5-20
S3C2400 RISC MICROPROCESSOR
MEMORY CONTROLLER
BANKSIZE REGISTER Register BANKSIZE Address 0x14000028 R/W R/W Description Flexible bank size register Reset Value 0x0
BANKSIZE SCLKEN
Bit [4]
Description SCLK is enabled only during SDRAM access cycle for reducing power consumption. When SDRAM isn't be accessed, SCLK is 'L' level. 0 = SCLK is always active 1 = SCLK is active only during the access (recommended) Not used BANK6/7 memory map 000 = 32M/32M 100 = 2M/2M 101 = 4M/4M 110 = 8M/8M 111 = 16M/16M
Initial State 0
Reserved BK76MAP
[3] [2:0]
0 000
5-21
MEMORY CONTROLLER
S3C2400 RISC MICROPROCESSOR
SDRAM MODE REGISTER SET REGISTER (MRSR) Register MRSRB6 MRSRB7 Address 0x1400002C 0x14000030 R/W R/W R/W Description Mode register set register bank6 Mode register set register bank7 Reset Value xxx xxx
MRSR Reserved WBL
Bit [11:10] [9] Not use Write burst length 0 = Burst(Fixed) 1 = reserved
Description
Initial State - x
TM
[8:7]
Test mode 00 = mode register set(Fixed) 01, 10, 11 = reserved CAS latency 000 = 1 clock, 010 = 2 clocks, the others : reserved Burst type 0 = sequential(Fixed) 1 = reserved Burst length 000 = 1(Fixed) the others = reserved 011=3 clocks
xx
CL
[6:4]
xxx
BT
[3]
x
BL
[2:0]
xxx
NOTE:
MRSR register must not be reconfigured while the code is running on SDRAM.
IMPORTANT NOTES 1. All 13 memory control registers have to be written using the STM instruction (not STMIA instruction). 2. In STOP mode/SL_IDLE mode, DRAM/SDRAM has to enter the DRAM/SDRAM self-refresh mode.
5-22
S3C2400 RISC MICROPROCESSOR
MEMORY CONTROLLER
NOTES
5-23
S3C2400 RISC MICROPROCESSOR
CLOCK & POWER MANAGEMENT
6
CLOCK & POWER MANAGEMENT
OVERVIEW
The clock & power management unit consists of 3 parts, clock control, USB control, and power control. The Clock control logic in S3C2400 can generate the required clock signals, FCLK for CPU, HCLK for the AHB bus peripherals, and PCLK for the APB bus peripherals. There are two PLL in S3C2400. One is for FCLK,HCLK, and PCLK, the other is dedicated for USB block (48MHz). The clock control logic can make slow clock without PLL and connect/disconnect the clock to each peripheral block by S/W, which will reduce the power consumption. In the power control logic, S3C2400 has various power management schemes to keep optimal power consumption for a given task. The power management in S3C2400 consists of five modes: NORMAL mode, SLOW mode, IDLE mode, STOP mode and SL_IDLE mode for the self-refresh mode LCD. NORMAL mode is used to supply clocks to CPU as well as all peripherals in S3C2400. In this case, the power consumption will be maximized when all peripherals are turned on. The user can control the operation of peripherals by S/W. For example, if a timer is not needed, the user can disconnect the clock to the timer to reduce power. SLOW mode is non-PLL mode. Unlike the Normal mode, the Slow mode uses an external clock (XTIpll or EXTCLK) directly as FCLK in S3C2400 without PLL. In this case, the power consumption depends on the frequency of the external clock only. The power consumption due to PLL itself is excluded. IDLE mode disconnects the clock (FCLK) only to CPU core while it supplies the clock to all peripherals. By using IDLE mode, power consumption due to CPU core can be reduced. Any interrupt request to CPU can wake-up from Idle mode. STOP mode freezes all clocks to the CPU as well as peripherals by disabling PLLs. The power consumption is only due to the leakage current in S3C2400, which is uA unit. The wake-up from STOP mode can be done by activating external interrupt pins or RTC alarm. SL_IDLE mode causes the LCD controller to work. In this case, the clock to CPU and all peripherals except LCD controller should be stopped, therefore, the power consumption in the SL_Idle mode is less than that in the Idle mode.
6-1
CLOCK & POWER MANAGEMENT
S3C2400 RISC MICROPROCESSOR
FUNCTION DESCRIPTION
CLOCK ARCHITECTURE Figure 6-1 shows a block diagram of the clock architecture. The main clock source comes from an external crystal(XTIpll) or external clock(EXTCLK). The clock generator consists of an oscillator block(Oscillation Amplifier) which is connected to an external crystal, and also has two PLLs (Phase-Locked-Loop) which generate the high frequency clock required in S3C2400.
CLOCK SOURCE SELECTION Table 6-1 shows the relationship between the combination of mode control pins (OM3 and OM2) and the selection of source clock for S3C2400. The OM[3:2] status is latched internally by referring the OM3 and OM2 pins at the rising edge of nRESET. Table 6-1. Clock source selection at boot-up Mode OM[3:2] 00 01 10 11 MPLL state On (1) On (1) On (1) On (1) UPLL state On (1) On (1) On (1) On (1) Main Clock source Crystal Crystal EXTCLK EXTCLK USB Clock source Crystal EXTCLK Crystal EXTCLK
NOTES: 1. Although the M(U)PLL starts just after a reset, the M(U)PLL output(Mpll,Upll) isn't used as the system clock until the S/W writes valid settings to the M(U)PLLCON register. Before this valid setting, the clock from external crystal or EXTCLK source will be used as the system clock directly. Even if the user wants to maintain the default value of MPLLCON register, the user should write the same value into M(U)PLLCON register. 2. OM[3:2] is used to determine test mode when OM[1:0] is 11.
6-2
S3C2400 RISC MICROPROCESSOR
CLOCK & POWER MANAGEMENT
XTIpll XTOpll EXTCLK
OSC MPLL Mpll CLKCNTL FCLK
HDIVN PDIVN
MPLL CLK UPLL CLK HCLK PCLK FCLK
Control Signal USBCNTL Upll UPLL
CLKOUT
FH P POWCNTL
P[5:0] M[7:0] S[1:0]
Power Management Block
Test mode OM[1:0]
UCLK
HCLK PCLK USB Host I/F H_USB TIC ExtMaster
FCLK Memory Controller
ARM920T
Interrupt Controller H_LCD LCD Controller
Bus Controller Arbitration DMA 4ch
WDT P_PWM PWM USB Device
I2 S P_I2 C P_I2 C I2C
MMC P_MMC P_GPIO GPIO
ADC P_ADC P_RTC RTC
UART(0,1) P_UART P_SPI SPI(0,1)
P_USB
Figure 6-1. Clock Generator Block Diagram
6-3
CLOCK & POWER MANAGEMENT
S3C2400 RISC MICROPROCESSOR
PLL (PHASE-LOCKED-LOOP) The MPLL within the clock generator is the circuit which synchronizes an output signal with a reference input signal in frequency and phase. In this application, it includes the following basic blocks (Figure 6-2 shows the clock generator block diagram); the VCO(Voltage Controlled Oscillator) to generate the output frequency proportional to input DC voltage, the divider P to divide the input frequency(Fin) by p, the divider M to divide the VCO output frequency by m which is input to PFD(Phase Frequency Detector), the divider S to divide the VCO output frequency by s which is Mpll(the output frequency from MPLL block), the phase difference detector, charge pump, and loop filter. The output clock frequency Mpll is related to the reference input clock frequency Fin by the following equation: Mpll = (m * Fin) / (p * 2s) m = M (the value for divider M)+ 8, p = P(the value for divider P) + 2 The UPLL within the clock generator is same as the MPLL in every aspect. The following sections describe the operation of the PLL, that includes the phase difference detector, charge pump, VCO (Voltage controlled oscillator), and loop filter. Phase Difference Detector(PFD) The PFD monitors the phase difference between the Fref (the reference frequency as shown in Fig. 6-2) and Fvco, and generates a control signal(tracking signal) when it detects a difference. Charge Pump(PUMP) The charge pump converts the PFD control signal into a proportional charge in voltage across the external filter that drives the VCO. Loop Filter The control signal that the PFD generates for the charge pump, may generate large excursions(ripples) each time the Fvco is compared to the Fref. To avoid overloading the VCO, a low pass filter samples and filters the highfrequency components out of the control signal. The filter is typically a single-pole RC filter consisting of a resistor and capacitor. A recommended capacitance in the external loop filter(Capacitance as shown in Figure 6-2) is 5 pF or above. Voltage Controlled Oscillator (VCO) The output voltage from the loop filter drives the VCO, which causes its oscillation frequency to increase or decrease linearly as a function of variations in average voltage. When the Fvco matches Fref in terms of frequency as well as phase, the PFD stops sending a control signal to the charge pump, which stabilizes the input voltage to the loop filter in turn. The VCO frequency then remains constant, and the PLL remains locked onto the system clock. Usual Conditions for PLL & Clock Generator The following conditions are generally used. Loop filter capacitance for UPLL/MPLL External X-tal frequency External capacitance used for X-tal
NOTE: Value could be changed.
5 pF 10 - 20 MHz (note) 15 - 22 pF
6-4
S3C2400 RISC MICROPROCESSOR
CLOCK & POWER MANAGEMENT
Fin
Divider P
Fref PFD PUMP
Loop Filter
P[5:0] Divider M Fv c o
R C VCO Internal M/UPLL CAP
M[7:0]
S[1:0]
Divider S
MPLL,UPLL
Figure 6-2. PLL (Phase-Locked Loop) Block Diagram
VDD EXTCLK External OSC VDD XTIpll XTIpll EXTCLK
XTOpll
XTOpll
a) X-TAL oscillation(OM[3:2]=00)
b) External clock source(OM[3:2]=11)
Figure 6-3. Main Oscillator Circuit Examples
6-5
CLOCK & POWER MANAGEMENT
S3C2400 RISC MICROPROCESSOR
CLOCK CONTROL LOGIC The clock control logic determines the clock source to be used, i.e., the PLL clock(Mpll) or the direct external clock(XTIpll or EXTCLK). When PLL is configured to a new frequency value, the clock control logic disables the FCLK until the PLL output is stabilized using the PLL locking time. The clock control logic is also activated at power-on reset and wake-up from power-down mode. PLL Lock Time The lock time is the minimum time required for PLL output stabilization. The lock time should be a minimum of 150us. After reset and wake-up from STOP and SL_IDLE mode, respectively, the lock-time is inserted automatically by the internal logic with lock time count register. The automatically inserted lock time is calculated as follows; t_lock(the PLL lock time by H/W logic) = (1/ Fin) x n, (n = M_LTIME,U_LTIME value) Power-On Reset(XTIpll) Figure 6-4 shows the clock behavior during the power-on reset sequence. The crystal oscillator begins oscillation within several milliseconds. When nRESET is released after the stabilization of OSC(XTIpll) clock, the PLL starts to operate according to the default PLL configuration. However PLL is commonly known to be unstable after power-on reset, so Fin fed directly to FCLK instead of the Mpll(PLL output) before the S/W newly configures the PLLCON. Even if the user wants to use the default value of PLLCON register after reset, user should write the same value into PLLCON register by S/W. The PLL begins the lockup sequence again toward the new frequency only after the S/W configures the PLL with a new frequency. FCLK can be configured to be PLL output (Mpll) immediately after lock time.
Power
nRESET
OSC (XTIpll) PLL is configured by S/W first time. Clock Disable lock time VCO is adapted to new clock frequency. VCO output
FCLK The logic operates by XTIpll FCLK is new frequency
Figure 6-4. Power-On Reset Sequence (When the external clock source is a crystal oscillator.)
6-6
S3C2400 RISC MICROPROCESSOR
CLOCK & POWER MANAGEMENT
Change PLL Settings In Normal Operation Mode During the operation of S3C2400 in NORMAL mode, if the user wants to change the frequency by writing the PMS value, the PLL lock time is automatically inserted. During the lock time, the clock is not supplied to the internal blocks in S3C2400. The timing diagram is as follow.
Mpll PMS setting PLL Lock-time FCLK It changes to new PLL clock after lock time automatically
Figure 6-5. Timing Diagram of Changing FCLK
NOTE: Changing PMS value can cause problem in LCD display. Because changed PMS value means changed CLKVAL of LCD control register. In this case, the user has to use SLOW mode like the below.
6-7
CLOCK & POWER MANAGEMENT
S3C2400 RISC MICROPROCESSOR
A CLK HCLK LCD Frame LCDCON1 Register CLKVAL LCDCON5 Register SLOWCLKSYNC CLKSLOW Register MPLL_OFF CLKSLOW Register SLOW_BIT (n-1)th frame
CLKVAL @SLOW(B CLK)
B CLK
C CLK
n-th frame
CLKVAL@NORMAL(C CLK)
(n+1)th frame
lock time
PMS setting
POWER MODE
NORMAL(A CLK)
SLOW(B CLK)
NORMAL(C CLK)
Figure 6-6. Timing Diagram of Changing PMS without the Interference of LCD Display
6-8
S3C2400 RISC MICROPROCESSOR
CLOCK & POWER MANAGEMENT
FCLK, HCLK, PCLK FCLK is used by ARM920T. HCLK is used for AHB bus which is used by ARM920T, the memory controller, the interrupt controller, LCD controller, the DMA and the USB host block. PCLK is used for APB bus which is used by the peripherals such as WDT,IIS,I2C,PWM timer, MMC interface, ADC, UART, GPIO, RTC and SPI. S3C2400 supports selection of Dividing Ratio between FCLK, HLCK and PCLK. This ratio is determined by HDIVN and PDIVN of CLKDIVN control register.
HDIVN 0 0 1 1
PDIVN 0 1 0 1
FCLK FCLK FCLK FCLK FCLK
HCLK FCLK FCLK FCLK / 2 FCLK / 2
PCLK FCLK FCLK / 2 FCLK / 2 FCLK / 4
Divide Ratio 1 : 1 : 1(Default) 1:1:2 1:2:2 1:2:4
When PMS value is set, CLKDIVN register should be set after PMS setting. These values of CLKDIVN are valid after PLL Lock-time. Which one of values is also available after reset and changing Power Management Mode. In other case, the setting value of CLKDIVN register is valid after 1.5 HCLK. But 1HCLK can be validated the value of CLKDIVN register changed from Default(1:1:1) to other Divide Ratio(1:1:2, 1:2:2 and 1:2:4)
FCLK CLKDIVN HCLK PCLK
1 HCLK 1.5 HCLK 1.5 HCLK 0x00000000 0x00000001(1:1:2) 0x00000003 (1:2:4) 0x00000000 (1:1:1)
Figure 6-7. Example that changes CLKDIVN register value
NOTE: CLKDIVN should be set carefully not to exceed the limit of HCLK & PCLK.
6-9
CLOCK & POWER MANAGEMENT
S3C2400 RISC MICROPROCESSOR
USB Clock Control USB host interface and USB device interface needs 48Mhz clock. In S3C2400, The USB dedicated PLL(UPLL) generates 48Mhz for USB. UCLK doesn't fed until the PLL(UPLL) is configured. USB PLL(UPLL) will be turned off during SL_IDLE mode or STOP mode automatically. Also, USB PLL(UPLL) will be turned on after exiting SL_IDLE mode or STOP mode if UCLK_ON bit is enabled in CLKSLOW register. Condition After reset After configuring UPLL UPLL is turned off by CLKSLOW register UPLL is turned on by CLKSLOW register UCLK state XTIPLL or EXTCLK L: during PLL lock time 48 MHz: after PLL lock time XTIPLL or EXTCLK 48 MHz UPLL state on on off on
POWER MANAGEMENT The power management block controls the system clocks by software for the reduction of power consumption in S3C2400. These schemes are related to PLL, clock control logic(FCLK,HCLK,PCLK) and wake-up signal. The Figure 6-8 depicts the clock distribution of S3C2400. S3C2400 has five power-down modes. The following section describes each power managing mode. The transition between the modes is not allowed freely. For available transitions among the modes, please refer to Figure 6-9.
6-10
S3C2400 RISC MICROPROCESSOR
CLOCK & POWER MANAGEMENT
CPUW RTCA PWRACK PWRMANOFF WKU
Module A GCLK MCLK 66 MHz SCLK Module A Module B
Module B PmsSet WakeUp P M S POWERDOWN POWERSLOW
Module A
Module B
Module A
Module B
Module A
Module B
Module A
Module B
Module A
Module B
Figure 6-8. The Clock Distribution Block Diagram
6-11
CLOCK & POWER MANAGEMENT
S3C2400 RISC MICROPROCESSOR
IDLE_BIT=1 & SL_IDLE_BIT=1 SL_IDLE EINT ,RTC alarm IDLE_BIT=1 IDLE RESET Interrupts, EINT, RTC alarm
NORMAL (SLOW_BIT=0) SLOW (SLOW_BIT=1)
Set IDLE_BIT=0 & STOP_BIT=0
EINT, RTC alarm (PLL is turned on automatically)
STOP_BIT=1
STOP
Figure 6-9. Power Management State Machine
Table 6-2. Functional Block Clock State In Each Power Mode Mode NORMAL IDLE SL_IDLE STOP SLOW ARM920T O X X X O AHB Modules (1), WDT O O X X O LCD SEL SEL O X SEL APB Modules (2), USB host SEL SEL X X
(3)
UCLK SEL SEL SEL X SEL
SEL
NOTES: 1. USB host and RTC are excluded. 2. WDT is excluded. 3. RTC interface is turned off in STOP mode but RTC Timer is always turned on. 4. SEL: selectable, O: turned on, X: turned off
6-12
S3C2400 RISC MICROPROCESSOR
CLOCK & POWER MANAGEMENT
6-13
CLOCK & POWER MANAGEMENT
S3C2400 RISC MICROPROCESSOR
NORMAL Mode In normal mode, all peripherals and the basic blocks(power management block, CPU core, bus controller, memory controller, interrupt controller, DMA, and external master) may operate fully. But, the clock to each peripheral, except the basic blocks, can be stopped selectively by S/W to reduce power consumption.
IDLE Mode In IDLE mode, the clock to CPU core is stopped except bus controller, memory controller, interrupt controller, and power management block. To exit IDLE mode, EINT, or RTC alarm interrupt, or the other interrupts should be activated. (If users are willing to use EINT, GPIO block has to be turned on before the activation).
STOP Mode In STOP mode, all clocks are stopped for minimum power consumption. Therefore, the PLL and oscillator circuit are also stopped. Just after exiting the STOP mode, only NORMAL mode is available. In Figure 6-9, the user must return from STOP mode to NORMAL mode. To exit from STOP mode, EINT or RTC alarm has to be activated and CLKCON register is set properly. -- DRAM has to be in self-refresh mode during STOP mode to retain valid memory data. -- LCD must be stopped before STOP mode, because DRAM can't be accessed when it's in self-refresh mode. -- All interrupts should be masked, because DRAM can't be accessed when it's in self-refresh mode. (Even though all interrupts are masked, EINT can wake-up S3C2400 with the setting of EXINT register.) -- If MMU is turned on, TLB fill operation should not be allowed after entering STOP mode because SDRAM is entered the self-refresh mode. So, The TLB should be filled in advance. Please refer to our reference code. The S3C2400 can exit from STOP mode by EINT(external interrupts) or RTC alarm. During the wake-up sequences, the crystal oscillator and PLL may begin to operate. The lock time is also needed to stabilize FCLK. The lock time is inserted automatically and guaranteed by power management logic. During this lock time the clock is not supplied. Just after wake-up sequences wake-up interrupt(RTC alarm or external interrupt) is requested.
6-14
S3C2400 RISC MICROPROCESSOR
CLOCK & POWER MANAGEMENT
XTIpll or EXTCLK Wake-up Clock Disable VCO Output several slow clocks (XTIpll or EXTCLK) FCLK STOP mode is initiated.
lock time
Figure 6-10. Entering STOP Mode and Exiting STOP mode (Wake-up)
6-15
CLOCK & POWER MANAGEMENT
S3C2400 RISC MICROPROCESSOR
SL_IDLE Mode (S_LCD Mode) In SL_IDLE mode, the clock to the basic blocks is stopped. Only the LCD controller is working to maintain the LCD screen. Less power is consumed in the SL_IDLE mode than in the IDLE mode. SDRAM has to be in self-refresh mode during SL_IDLE mode to retain the valid data in DRAM. Procedure for entering SL_IDLE Mode. 1. 2. 3. 4. Mask all interrupts. Check the LCD line counter(LINECNT) whether or not sufficient time is remained until entering SLOW mode. LCD frame should not be changed until STEP 4. Set SLOWCLKSYNC bit in LCD control register Wait until the LCD line counter reaches the self-refresh line. (The LCDCON5:SELFREF bit should be enabled at 4n+1th line to enable the LCD self-refresh at 4n+0th line.) At the moment that the LCD line reaches the LCD selfrefresh line, turn on LCDCON5:SELFREF bit. Reconfigure LCDCON1 for SLOW clock. These new parameter will be effective from next LCD frame. LCDCON2,3,4 can't be changed. Wait until the LCD self-refresh command is effective. Turn on SLOW mode. The SLOW mode will not be effective until the current LCD frame is completed. As TLB fill operation can't be occurred after SDRAM self-refresh mode is effective. So, fill the TLB in advance like our example code. Wait until the line counter reaches 0.
5. 6. 7. 8. 9.
10. While the line counter is 0, SL_IDLE mode should be enabled by setting CLKCON resister. 11. Wait while the line counter is 0. 12. The SL_IDLE mode will be effective just after the current frame is completed. Procedure for Exiting from SL_IDLE Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. SL_IDLE mode is woken up by EINT or alarm interrupt. Just after wake-up, the operating mode is SLOW mode. change the CLKCON as normal mode(Actually, SLOW mode). Check the LCD line counter whether sufficient time is remained or not until exiting SLOW mode. LCD frame should not be changed until STEP 4. Turn on MPLL if the MPLL is turned off. Configure LCD parameters for NORMAL clock. These new parameter will be effective from next LCD frame. Wait until the line counter is 0. Turn off SLOW mode. The NORMAL mode will not be effective until the current LCD frame is completed. Wait until the current frame is completed. Clear SLOWCLKSYNC bit in LCD control register.
10. Wait until NORMAL mode is effective by polling the LCD line counter. 11. Wait until the LCD line counter reaches the self-refresh line. (The LCDCON5:SELFREF bit should be disabled at 4n+1th line to disable the LCD self-refresh at 4n+0th line.) At the moment that the LCD line reaches the LCD selfrefresh line, turn off LCDCON5:SELFREF bit. 12. Unmask interrupts. The interrupt(wake-up source) will be generated.
6-16
S3C2400 RISC MICROPROCESSOR
CLOCK & POWER MANAGEMENT
HCLK
LINECNT==0
LCD frame LCDCON1 Register CLKVAL LCDCON5 Register SLOWCLKSYNC Set CLKCON Register to SL_IDLE mode CLKSLOW Register MPLL_OFF CLKSLOW Register SLOW_BIT LCDCON5 Register SELFREF POWER MODE
(n-1)th frame
CLKVAL@SLOW and SL_IDLE mode
n-th frame
m-th frame
(m+1)th frame
CLKVAL@NORMAL mode
by S/W
wake up by S/W lock time
NORMAL
SL-IDLE
SLOW
NORMAL
Figure 6-11. Entering SL_IDLE Mode and Exiting from SL_IDLE Mode (Wake-up)
6-17
CLOCK & POWER MANAGEMENT
S3C2400 RISC MICROPROCESSOR
SLOW Mode (Non-PLL Mode) Power consumption can be reduced in the SLOW mode by applying a slow clock and excluding the power consumption from the PLL, itself. The FCLK is the frequency of divide_by_n of the input clock(XTIpll or EXTCLK) without PLL. The divider ratio is determined by SLOW_VAL in the CLKSLOW control register and CLKDIVN control register. Table 6-3. CLKSLOW and CLKDIVN Register Settings for SLOW Clock SLOW_VAL FCLK HCLK 1/1 Option (HDIVN=0) 000 001 010 011 100 101 110 111 EXTCLK or XTIpll / 1 EXTCLK or XTIpll / 2 EXTCLK or XTIpll / 4 EXTCLK or XTIpll / 6 EXTCLK or XTIpll / 8 EXTCLK or XTIpll / 10 EXTCLK or XTIpll / 12 EXTCLK or XTIpll / 14 EXTCLK or XTIpll / 1 EXTCLK or XTIpll / 2 EXTCLK or XTIpll / 4 EXTCLK or XTIpll / 6 EXTCLK or XTIpll / 8 EXTCLK or XTIpll / 10 EXTCLK or XTIpll / 12 EXTCLK or XTIpll / 14 1/2 Option (HDIVN=1) EXTCLK or XTIpll / 2 EXTCLK or XTIpll / 4 EXTCLK or XTIpll / 8 EXTCLK or XTIpll / 12 EXTCLK or XTIpll / 16 EXTCLK or XTIpll / 20 EXTCLK or XTIpll / 24 EXTCLK or XTIpll / 28 PCLK 1/1 Option (PDIVN=0) HCLK HCLK HCLK HCLK HCLK HCLK HCLK HCLK 1/2 Option (PDIVN=1) HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 48MHz 48MHz 48MHz 48MHz 48MHz 48MHz 48MHz 48MHz UCLK
In SLOW mode, the PLL will be turned off to reduce the PLL power consumption. When PLL is turned off in SLOW mode and users change power mode from SLOW mode to NORMAL mode, the PLL needs clock stabilization time(PLL lock time). This PLL stabilization time is automatically inserted by the internal logic with lock time count register. The PLL stability time will take 150us after PLL is turn on. During PLL lock time, the FCLK is SLOW clock. Users can change the frequency by enabling SLOW mode bit in CLKSLOW register in PLL on state. The SLOW clock is generated during SLOW mode. The timing diagram is in Figure 6-12.
6-18
S3C2400 RISC MICROPROCESSOR
CLOCK & POWER MANAGEMENT
Mpll SLOW_BIT MPLL_OFF FCLK Divided external clock It changes to PLL clock after slow mode off Slow mode enable Slow mode disable
Figure 6-12. The case that Exit_from_Slow_mode command is issued in PLL on state
6-19
CLOCK & POWER MANAGEMENT
S3C2400 RISC MICROPROCESSOR
If users exit from SLOW mode to Normal mode by disabling the SLOW_BIT in the CLKSLOW register after PLL lock time, the frequency is changed just after SLOW mode is disabled. The timing diagram is in Figure 6-13.
S/W lock time Mpll SLOW_BIT MPLL_OFF FCLK Divided OSC clock It changes to PLL clock after slow mode off Slow mode enable PLL off Slow mode disable PLL on
Figure 6-13. The Case that Exit_from_Slow_Mode Command is Issued after Lock Time is End If users exit from SLOW mode to Normal mode by disabling SLOW_BIT and MPLL_OFF bit simultaneously in CLKSLOW register, the frequency is changed just after the PLL lock time. The timing diagram is as follow.
H/W lock time Mpll SLOW_BIT MPLL_OFF FCLK Divided OSC clock It changes to PLL clock after lock time automatically Slow mode enable PLL off Slow mode disable PLL on
Figure 6-14. The Case that the Exit_from_Slow_Mode Command and the Instant PLL_on Command is Issued Aimultaneously
6-20
S3C2400 RISC MICROPROCESSOR
CLOCK & POWER MANAGEMENT
Wake-Up from STOP Mode When the S3C2400 is woken up from power down mode(STOP mode) by an EINT or a RTC alarm interrupt, the PLL is turned on automatically. But S3C2400 is not in NORMAL mode yet. Because the configuration of the CLKCON is ignored. So, the user has to set CLKCON register. After the wake-up from STOP mode, the processor is not in NORMAL mode as explained above. The new value, which reflects the new state, has to be re-written into the CLKCON register. Eventually, the processor state will be changed from STOP mode to Normal mode. Table 6-4. The Status of PLL and FCLK After Wake-Up Mode before Wake-up STOP SL_IDLE IDLE Signaling EINT For Wake-Up The S3C2400 can be woken up from SL_IDLE mode or STOP mode only if the following conditions are met. a) Level signal(H or L) or edge signal(rising or falling or both) is asserted on EINTn input pin. b) EINTn pin has to be configured as EINT in the GPIO control register. It is important to configure the EINTn in the GPIO control register as an external interrupt pins. For wake-up, we need H/L level or rising/falling edge or both edge signals on EINTn pin. Just after wake-up the corresponding EINTn pin will not be used for wake-up. This means that these pins can be used as external interrupt request pins again. PLL On/Off after Wake- up off on off unchanged FCLK after Wake-up and before the Lock Time no clock SLOW clock (the PLL lock time is issued by S/W) unchanged FCLK after the Lock Time by Internal Logic normal mode clock unchanged unchanged
Entering IDLE Mode If CLKCON[2] is set to 1 to enter the IDLE mode, S3C2400 will enter into IDLE mode after some delay(until when the power control logic receives ACK signal from the CPU wrapper).
PLL On/Off The PLL can only be turned off for power saving in slow mode. If PLL is turned off in any other mode, MCU operation is not guaranteed. When the processor is in SLOW mode and tries to change its state into other state requiring that PLL be turned on, then SLOW_BIT should be clear to move to another state after PLL stabilization.
6-21
CLOCK & POWER MANAGEMENT
S3C2400 RISC MICROPROCESSOR
PnUPs Register and STOP/SL_IDLE Mode In STOP mode, the data bus(D[31:0] or D[15:0] ) is Hi-z state. But, because of the characteristics of I/O pad, the data bus pull-up resistors have to be turned on to reduce the power consumption in STOP/SL_IDLE mode. D[31:16] pin pull-up resistors can be controlled by GPIO control registers. D[15:0] pin pull-up resistors can be controlled by the GPIO control register.
OUTPUT PORT State and STOP/SL_IDLE mode If output is L, the current will be consumed through the internal parasitic resistance; if the output is H, the current will not be consumed. If a port is configured as an output port, the current consumption can be reduced if the output state is H. The output ports are recommended to be in H state to reduce STOP mode current consumption.
ADC Power Down The ADC has an additional power-down bit(STDBM) in ADCCON. If S3C2400 enters the STOP mode, the ADC should enter it's own power-down mode.
6-22
S3C2400 RISC MICROPROCESSOR
CLOCK & POWER MANAGEMENT
CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER
LOCK TIME COUNT REGISTER (LOCKTIME) Register LOCKTIME Address 0x14800000 R/W R/W Description PLL lock time count register Reset Value 0x00ffffff
LOCKTIME U_LTIME M_LTIME
Bit [23:12] [11:0]
Description UPLL lock time count value for UCLK. (U_LTIME>150uS) MPLL lock time count value for FCLK,HCLK,PCLK (M_LTIME>150uS)
Initial State 0xfff 0xfff
PLL CONTROL REGISTER (MPLLCON, UPLLCON) Mpll = (m * Fin) / (p * 2s) m = (MDIV + 8), p = (PDIV + 2), s = SDIV Example If Fin=14.318Mhz and FCLK=60Mhz, the calculated value is as follows; MDIV=59, PDIV=6 and SDIV=1 (This value may be calculated using PLLSET.EXE utility, provided by SAMSUNG.)
PLL VALUE SELECTION GUIDE 1. 2. 3. Mpll * 2s has to be less than 300 MHz. S should be as great as possible. (Fin / p) is recommended to be the value between 2MHz - 3MHz. But, you had better choose the value which is close to 2MHz. Register MPLLCON UPLLCON Address 0x14800004 0x14800008 R/W R/W R/W Description MPLL configuration register UPLL configuration register Reset Value 0x0005c080 0x00028080
PLLCON MDIV PDIV SDIV
Bit [19:12] [9:4] [1:0] Main divider control Pre-divider control Post divider control
Description
Initial State 0x5c/0x28 0x08/0x08 0x0/0x0
Caution: When you set MPLL&UPLL values simultaneously, MPLL value MPLL value first and then UPLL value should be set.
6-23
CLOCK & POWER MANAGEMENT
S3C2400 RISC MICROPROCESSOR
CLOCK CONTROL REGISTER (CLKCON) Register CLKCON Address 0x1480000C R/W R/W Description Clock generator control Register Reset Value 0xfff8
CLKCON SPI IIS IIC ADC RTC
Bit [15] [14] [13] [12] [11]
Description Controls PCLK into SPI block 0 = Disable, 1 = Enable Controls PCLK into IIS block 0 = Disable, 1 = Enable Controls PCLK into IIC block 0 = Disable, 1 = Enable Controls PCLK into ADC block 0 = Disable, 1 = Enable Controls PCLK into RTC control block. Even if this bit is cleared to 0, RTC timer is alive. 0 = Disable, 1 = Enable Controls PCLK into GPIO block 0 = Disable, 1 = Enable Controls PCLK into UART1 block 0 = Disable, 1 = Enable Controls PCLK into UART0 block 0 = Disable, 1 = Enable Controls PCLK into MMC interface block 0 = Disable, 1 = Enable Controls PCLK into PWMTIMER block 0 = Disable, 1 = Enable Controls PCLK into USB device block 0 = Disable, 1 = Enable Controls HCLK into USB host block 0 = Disable, 1 = Enable Controls HCLK into LCDC block 0 = Disable, 1 = Enable Enters IDLE mode. This bit isn't be cleared automatically. 0 = Disable, 1 = Transition to IDLE(SL_IDLE) mode SL_IDLE mode option. This bit isn't be cleared automatically. 0 = Disable, 1 = SL_IDLE mode. To enter SL_IDLE mode, CLKCON register has to be 0xe.
Initial State 1 1 1 1 1
GPIO UART1 UART0 MMC PWMTIMER USB device USB host LCDC IDLE BIT SL_IDLE
[10] [9] [8] [7] [6] [5] [4] [3] [2] [1]
1 1 1 1 1 1 1 1 0 0
STOP BIT
[0]
Enters STOP mode. This bit isn't be cleared automatically. 0 = Disable 1 = Transition to STOP mode
0
6-24
S3C2400 RISC MICROPROCESSOR
CLOCK & POWER MANAGEMENT
CLOCK SLOW CONTROL REGISTER (CLKSLOW) Register CLKSLOW Address 0x14800010 R/W R/W Description Slow clock control register Reset Value 0x00000004
CLKSLOW UCLK_ON
Bit [7]
Description 0 = UCLK ON (UPLL is also turned on and the UPLL lock time is inserted automatically.) 1 = UCLK OFF(UPLL is also turned off) Reserved 0 = PLL is turned on. After PLL stabilization time (minimum 150us), SLOW_BIT can be cleared to 0. 1 = PLL is turned off. PLL is turned off only when SLOW_BIT is 1. 0 = FCLK = Mpll (MPLL output) 1 = SLOW mode FCLK = input clock / (2 x SLOW_VAL) (SLOW_VAL > 0) FCLK = input clock (SLOW_VAL = 0) input clock = XTIpll or EXTCLK The divider value for the slow clock when SLOW_BIT is on.
Initial State 0
Reserved MPLL_OFF
[6] [5]
- 0
SLOW_BIT
[4]
0
SLOW_VAL
[2:0]
0x4
CLOCK DIVIDER CONTROL REGISTER (CLKDIVN) Register CLKDIVN Address 0x14800014 R/W R/W Description Clock divider control register Reset Value 0x00000000
CLKDIVN HDIVN PDIVN
Bit [1] [0]
Description 0 = HCLK has the clock same as the FCLK 1 = HCLK has the clock same as the FCLK/2 0 = PCLK has the clock same as the HCLK 1 = PCLK has the clock same as the HCLK/2
Initial State 0 0
6-25
S3C2400 RISC MICROPROCESSOR
CPU WRAPPER & BUS PRIORITIES
7
1. 2. 3. 4. 5. 6. 7. 8. 9.
BUS PRIORITIES
OVERVIEW
The bus arbitration logic determines the priorities of bus masters. It supports a combination of rotation priority mode and fixed priority mode.
BUS PRIORITY MAP In S3C2400, there are eleven bus masters, i.e., DRAM refresh controller, LCD_DMA, DMA0, DMA1, DMA2, DMA3, USB_HOST_DMA, EXT_BUS_MASTER, TIC (Test interface controller), and ARM920T. The priorities among these bus masters after a reset are as follows: DRAM refresh controller LCD_DMA DMA0 DMA1 DMA2 DMA3 USB host DMA External bus master TIC
10. ARM920T 11. reserved Among those bus masters, four DMAs operate under the rotation priority, while others run under the fixed priority.
7-1
BUS PRIORITIES
S3C2400 RISC MICROPROCESSOR
NOTES
7-2
S3C2400 RISC MICROPROCESSOR
DMA
8
DMA
OVERVIEW
S3C2400 supports four-channel DMA controller that is located between the system bus and the peripheral bus. Each channel of DMA controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions. In other words, each channel can handle the following four cases: 1) both source and destination are in the system bus, 2) source is in the system bus while destination is in the peripheral bus, 3) source is in the peripheral bus while destination is in the system bus, 4) both source and destination are in the peripheral bus. The main advantage of DMA is that it can transfer the data without CPU intervention. The operation of DMA can be initiated by S/W, the request from internal peripherals or the external request pins.
8-1
DMA
S3C2400 RISC MICROPROCESSOR
DMA REQUEST SOURCES
Each channel of DMA controller can select one of DMA request source among four DMA sources if H/W DMA request mode is selected by DCON register. (Note that if S/W request mode is selected, this DMA request sources have no meaning at all.) The four DMA sources for each channel are as follows. Table 8-1. DMA request sources for each channel Source0 Ch-0 Ch-1 Ch-2 Ch-3 nXDREQ0 nXDREQ1 I2SSDO USB device Source1 UART0 UART1 I2SSDI MMC Source2 MMC I2SSDI MMC SPI Source3 Timer SPI Timer Timer
Here, nXDREQ0 and nXDREQ1 represent two external sources(External Devices), and I2SSDO and I2SSDI represent IIS transmitting and receiving, respectively.
DMA OPERATION
The details of DMA operation can be explained using three-state FSM(finite state machine) as follows: State-1. State-2. State-3. As an initial state, it waits for the DMA request. If it comes, go to state-2. At this state, DMA ACK and INT REQ are 0. In this state, DMA ACK becomes 1 and the counter(CURR_TC) is loaded from DCON[19:0] register. Note that DMA ACK becomes 1 and remains 1 until it is cleared later. In this state, sub-FSM handling the atomic operation of DMA is initiated. The sub-FSM reads the data from the source address and then writes it to destination address. In this operation, data size and transfer size (single or burst) are considered. This operation is repeated until the counter(CURR_TC) becomes 0 in the whole service mode, while performed only once in a single service mode. The main FSM (this FSM) counts down the CURR_TC when the sub-FSM finishes each of atomic operation. In addition, this main FSM asserts the INT REQ signal when CURR_TC becomes 0 and the interrupt setting of DCON[28] register is set to 1. In addition, it clears DMA ACK if one of the following conditions are met. 1) CURR_TC becomes 0 in the whole service mode 2) atomic operation finishes in the single service mode.
Note that in the single service mode, these three states of main FSM are performed and then stops, and waits for another DMA REQ. And if DMA REQ comes in all three states are repeated. Therefore, DMA ACK is asserted and then de-asserted for each atomic transfer. In contrast, in the whole service mode, main FSM waits at state-3 until CURR_TC becomes 0. Therefore, DMA ACK is asserted during all the transfers and then de-asserted when TC reaches 0. However, INT REQ is asserted only if CURR_TC becomes 0 regardless of the service mode (single service mode or whole service mode).
8-2
S3C2400 RISC MICROPROCESSOR
DMA
EXTERNAL DMA DREQ/DACK PROTOCOL There are four types of external DMA request/acknowledge protocols. Each type defines how the signals like DMA request and acknowledge are related to these protocols.
Basic DMA Timing The DMA service means paired Reads and Writes cycles during DMA operation, which is one DMA operation. The Figure 8-1 shows the basic Timing in the DMA operation of the S3C2400. -- The setup time and the delay time of XnXDREQ and XnXDACK are same in all the modes. -- If the completion of XnXDREQ meets its setup time, it is synchronized twice and then XnXDACK is asserted. -- After assertion of XnXDACK, DMA requests the bus and if it gets the bus it performs its operations. XnXDACK is deasserted when DMA operation finishes.
XSCLK 9.3ns Setup XnXDREQ Min. 2MCLK XnXDACK ~ ~ ~ ~ 6.8ns Delay Min. 3MCLK Read Write 6.6ns Delay 9.3ns Setup
Figure 8-1. Basic DMA Timing Diagram
8-3
DMA
S3C2400 RISC MICROPROCESSOR
Demand/Handshake Mode Comparison
- Related to the Protocol between XnXDREQ and XnXDACK
These are two different modes related to the protocol between XnXDREQ and XnXDACK. Fig. 8-2 shows the differences between these two modes i.e., Demand and Handshake modes. At the end of one transfer(Single/Burst transfer), DMA checks the state of double-synched XnXDREQ. Demand mode -- If XnXDREQ remains asserted, the next transfer starts immediately. Otherwise it waits for XnXDREQ to be asserted. Handshake mode -- If XnXDREQ is deasserted, DMA deasserts XnXDACK in 2cycles. Otherwise it waits until XnXDREQ is deasserted. Caution : XnXDREQ has to be asserted(low) only after the deassertion(high) of XnXDACK.
XSCLK Demand Mode XnXDREQ 2 cycles 1st Transfer XnXDACK ~ ~ ~ ~ ~ ~ ~ ~ Min. 2MCLK Read BUS Acquisition Handshake Mode XnXDREQ ~ ~ Read XnXDACK Min. 2MCLK ~ ~ Write Write Read Write 2nd Transfer
Actual Transfer
Figure 8-2. Demand/Handshake Mode Comparison
8-4
S3C2400 RISC MICROPROCESSOR
DMA
Transfer Size -- There are two different transfer sizes; single and Burst 4. -- DMA holds the bus firmly during the transfer of these chunk of data, thus other bus masters can not get the bus. Burst 4 Transfer Size 4 sequential Reads and 4 sequential Writes are performed in the Burst 4 Transfer.
NOTE: Single Transfer size : One read and one write are performed.
XSCLK
XnXDREQ
XnXDACK Min. 2MCLK
3 cycles Read Read Read Read Write ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Write ~ ~ Write Write ~ ~ ~ ~
Figure 8-3. Burst 4 Transfer Size
8-5
DMA
S3C2400 RISC MICROPROCESSOR
EXAMPLES OF POSSIBLE CASES Single service, Demand Mode, Single Transfer Size The assertion of XnXDREQ is need for every unit transfer(Single service mode), the operation continues while the XnXDREQ is asserted(Demand mode), and one pair of Read and Write(Single transfer size) is performed.
XSCLK
XnXDREQ
XnXDACK Min. 2MCLK Read ~ ~ Write ~ ~ Read ~ ~ Write ~ ~
Figure 8-4. Single service, Demand Mode, Single Transfer Size Single service/Handshake Mode, Single Transfer Size
XSCLK
XnXDREQ
XnXDACK Min. 2MCLK Read ~ ~ Write ~ ~ Read ~ ~ Write ~ ~
Figure 8-5. Single Service, Handshake Mode, Single Transfer Size Whole service/Handshake Mode, Single Transfer Size
XSCLK
XnXDREQ
XnXDACK ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Double synch 3 cycles Read Write 2 cycles Read Write 2 cycles Read Write
Figure 8-6. Whole Service, Handshake Mode, Single Transfer Size
8-6
S3C2400 RISC MICROPROCESSOR
DMA
DMA SPECIAL REGISTERS
There are seven control registers for each DMA channel. (Since there are four channels, the total number of control registers is 28.) Four of them are to control the DMA transfer, and other three are to see the status of DMA controller. The details of those registers are as follows.
DMA INITIAL SOURCE REGISTER (DISRC) Register DISRC0 DISRC1 DISRC2 DISRC3 Address 0x14600000 0x14600020 0x14600040 0x14600060 R/W R/W R/W R/W R/W Description DMA 0 Initial Source Register DMA 1 Initial Source Register DMA 2 Initial Source Register DMA 3 Initial Source Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000
DISRCn LOC
Bit [30]
Description Bit 30 is used to select the location of source. 0 = the source is in the system bus (AHB), 1 = the source is in the peripheral bus (APB) Bit 29 is used to select the address increment. 0 = Increment 1= Fixed If it is 0, the address is increased by its data size after each transfer in burst and single transfer mode. If it is 1, the address is not changed after the transfer (In the burst mode, address is increased during the burst transfer, but the address is recovered to its first value after the transfer).
Initial State 0
INC
[29]
0
S_ADDR
[28:0]
These bits are the base address (start address) of source data to transfer. This value will be loaded into CURR_SRC only if the CURR_SRC is 0 and the DMA ACK is 1.
0x00000000
8-7
DMA
S3C2400 RISC MICROPROCESSOR
DMA INITIAL DESTINATION REGISTER (DIDST) Register DIDST0 DIDST1 DIDST2 DIDST3 Address 0x14600004 0x14600024 0x14600044 0x14600064 R/W R/W R/W R/W R/W Description DMA 0 Initial Destination Register DMA 1 Initial Destination Register DMA 2 Initial Destination Register DMA 3 Initial Destination Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000
DIDSTn LOC
Bit [30]
Description Bit 30 is used to select the location of destination. 0 = the destination is in the system bus (AHB). 1 = the destination is in the peripheral bus (APB). Bit 29 is used to select the address increment. 0 = Increment 1= Fixed If it is 0, the address is increased by its data size after each transfer in burst and single transfer mode. If it is 1, the address is not changed after the transfer (In the burst mode, address is increased during the burst transfer, but the address is recovered to its first value after the transfer).
Initial State 0
INC
[29]
0
D_ADDR
[28:0]
These bits are the base address (start address) of destination for the transfer. This value will be loaded into CURR_SRC only if the CURR_SRC is 0 and the DMA ACK is 1.
0x00000000
8-8
S3C2400 RISC MICROPROCESSOR
DMA
DMA CONTROL REGISTER (DCON) Register DCON0 DCON1 DCON2 DCON3 Address 0x14600008 0x14600028 0x14600048 0x14600068 R/W R/W R/W R/W R/W Description DMA 0 Control Register DMA 1 Control Register DMA 2 Control Register DMA 3 Control Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000
DCONn DMD_HS
Bit [30]
Description Select one between demand mode and handshake mode. 0 = demand mode is selected 1 = handshake mode is selected. In both modes, DMA controller starts its transfer and asserts DACK for a given asserted DREQ. The difference between two modes is whether it waits for the de-asserted DACK or not. In handshake mode, DMA controller waits for the de-asserted DREQ before starting a new transfer. If it sees the de-asserted DREQ, it de-asserts DACK and waits for another asserted DREQ. In contrast, in the demand mode, DMA controller does not wait until the DREQ is de-asserted. It just de-asserts DACK and then starts another transfer if DREQ is asserted. We recommend using handshake mode for external DMA request sources to prevent unintended starts of new transfers.
Initial State 0
SYNC
[29]
Select DREQ/DACK synchronization. 0 = DREQ and DACK are synchronized to PCLK (APB clock). 1 = DREQ and DACK are synchronized to HCLK (AHB clock). Therefore, devices attached to AHB system bus, this bit has to be set to 1, while those attached to APB system, it should be set to 0. For the devices attached to external system, user should select this bit depending on whether the external system is synchronized with AHB system or APB system.
0
INT
[28]
Enable/Disable the interrupt setting for CURR_TC(terminal count) 0 = CURR_TC interrupt is disabled. user has to look the transfer count in the status register. (i.e., polling) 1 = interrupt request is generated when all the transfer is done (i.e., CURR_TC becomes 0). Select the transfer size of an atomic transfer (i.e., transfer performed at each time DMA owns the bus before releasing the bus). 0 = a unit transfer is performed. 1 = a burst transfer of length four is performed.
0
TSZ
[27]
0
8-9
S3C2400 RISC MICROPROCESSOR
DMA
DCONn SERVMODE
Bit [26]
Description Select the service mode between single service mode and whole service mode. 0: single service mode is selected in which after each atomic transfer (single or burst of length four) DMA stops and waits for another DMA request. 1: whole service mode is selected in which one request gets atomic transfers to be repeated until the transfer count reaches to 0. In this mode, additional request is not required. Here, note that even in the whole service mode, DMA releases the bus after each atomic transfer and then tries to re-get the bus to prevent starving of other bus masters. Select DMA request source for each DMA. DCON0: 00: nXDREQ0 01:UART0 DCON1: 00: nXDREQ1 01:UART1 DCON2: 00:I2SSDO 01:I2SSDI DCON3: 00:USB device 01:MMC 10:MMC 10:I2SSDI 10:MMC 10:SPI 11:Timer 11:SPI 11:Timer 11:Timer
Initial State 0
HWSRCSEL
[25:24]
00
This bits control the 4-1 MUX to select the DMA request source of each DMA. These bits have meanings if and only if H/W request mode is selected by DCONn[23]. SWHW_SEL [23] Select the DMA source between software (S/W request mode) and hardware (H/W request mode). 0: S/W request mode is selected and DMA is triggered by setting SW_TRIG bit of DMASKTRIG control register. 1: DMA source selected by bit[25:24] is used to trigger the DMA operation. Set the reload on/off option. 0 = auto reload is performed when a current value of transfer count becomes 0 (i.e., all the required transfers are performed). 1 = DMA channel(DMA REQ) is turned off when a current value of transfer count becomes 0. The channel on/off bit(DMASKTRIGn[1]) is set to 0(DREQ off) to prevent unintended further start of new DMA operation Data size to be transferred. 00 = Byte 01 = Half word 10 = Word 11 = reserved Initial transfer count (or transfer beat). Note that the actual number of bytes that are transferred is computed by the following equation: DSZ x TSZ x TC, where DSZ, TSZ, and TC represent data size (DCONn[21:20]), transfer size (DCONn[27]), and initial transfer count, respectively. This value will be loaded into CURR_SRC only if the CURR_SRC is 0 and the DMA ACK is 1. 0
RELOAD
[22]
0
DSZ
[21:20]
00
TC
[19:0]
00000
8-10
S3C2400 RISC MICROPROCESSOR
DMA
DMA STATUS REGISTER (DSTAT) Register DSTAT0 DSTAT1 DSTAT2 DSTAT3 Address 0x1460000c 0x1460002c 0x1460004c 0x1460006c R/W R R R R Description DMA 0 Count Register DMA 1 Count Register DMA 2 Count Register DMA 3 Count Register Reset Value 000000h 000000h 000000h 000000h
DSTATn STAT
Bit [21:20]
Description Status of this DMA controller. 00 = It indicates that DMA controller is ready for another DMA request. 01 = It indicates that DMA controller is busy for transfers. Current value of transfer count. Note that transfer count is initially set to the value of DCONn[19:0] register and decreased by one at the end of every atomic transfer.
Initial State 00b
CURR_TC
[19:0]
00000h
8-11
DMA
S3C2400 RISC MICROPROCESSOR
DMA CURRENT SOURCE REGISTER (DCSRC) Register DCSRC0 DCSRC1 DCSRC2 DCSRC3 Address 0x14600010 0x14600030 0x14600050 0x14600070 R/W R R R R Description DMA 0 Current Source Register DMA 1 Current Source Register DMA 2 Current Source Register DMA 3 Current Source Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000
DCSRCn CURR_SRC
Bit [28:0]
Description Current source address for DMAn.
Initial State 0x00000000
CURRENT DESTINATION REGISTER (DCDST) Register DCDST0 DCDST1 DCDST2 DCDST3 Address 0x14600014 0x14600034 0x14600054 0x14600074 R/W R R R R Description DMA 0 Current Destination Register DMA 1 Current Destination Register DMA 2 Current Destination Register DMA 3 Current Destination Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000
DCDSTn CURR_DST
Bit [28:0]
Description Current destination address for DMAn.
Initial State 0x00000000
8-12
S3C2400 RISC MICROPROCESSOR
DMA
DMA MASK TRIGGER REGISTER (DMASKTRIG) Register DMASKTRIG0 DMASKTRIG1 DMASKTRIG2 DMASKTRIG3 Address 0x14600018 0x14600038 0x14600058 0x14600078 R/W R/W R/W R/W R/W Description DMA 0 Mask Trigger Register DMA 1 Mask Trigger Register DMA 2 Mask Trigger Register DMA 3 Mask Trigger Register Reset Value 000 000 000 000
DMASKTRIGn STOP
Bit [2]
Description Stop the DMA operation. 1 = DMA stops as soon as the current atomic transfer ends. If there is no current running atomic transfer, DMA stops immediately. The CURR_TC, CURR_SRC, CURR_DST will be 0.
NOTE: Due to possible current atomic transfer, "stop" may take several cycles. The finish of "stopping" operation (i.e., actual stop time) can be detected by waiting until the channel on/off bit(DMASKTRIGn[1]) is set to off. This stop is "actual stop".
Initial State 0
ON_OFF
[1]
DMA channel on/off bit. 0 = DMA channel is turned off. (DMA request to this channel is ignored.) 1 = DMA channel is turned on and the DMA request is handled. This bit is automatically set to off if we set the DCONn[22] bit to "no auto reload" and/or STOP bit of DMASKTRIGn to "stop". Note that when DCON[22] bit is "no auto reload", this bit becomes 0 when CURR_TC reaches 0. If the STOP bit is 1, this bit becomes 0 as soon as the current atomic transfer finishes.
NOTE: This bit should not be changed manually during DMA operations (i.e., this has to be changed only by using DCON[22] or STOP bit.)
0
SW_TRIG
[0]
Trigger the DMA channel in S/W request mode. 1 = it requests a DMA operation to this controller. However, note that for this trigger to have effects S/W request mode has to be selected (DCONn[23]) and channel ON_OFF bit has to be set to 1 (channel on). When DMA operation starts, this bit is cleared automatically.
0
NOTE:
You can freely change the values of DISRC register, DIDST registers, and TC field of DCON register. Those changes take effect only after the FINISH of current transfer (i.e., when CURR_TC becomes 0). On the other hand, any change made to other registers and/or fields takes immediate effect. Therefore, be careful in changing those registers and fields.
8-13
DMA
S3C2400 RISC MICROPROCESSOR
NOTES
8-14
S3C2400 RISC MICROPROCESSOR
I/O PORTS
9
I/O PORTS
OVERVIEW
S3C2400 has 90 multi-functional input/output port pins. There are seven ports: -- One 18-bit output ports. (Port A) -- Two 16-bit input/output ports. (Port B and C) -- One 11-bit input/output port. (Port D) -- One 12-bit input/output port. (Port E) -- One 7-bit input/output port. (Port F) -- One 10-bit input/output port. (Port G) Each port can be easily configured by software to meet various system configuration and design requirements. You have to define which function of each pin is used before starting the main program. If the multiplexed functions on a pin are not used, the pin can be configured as I/O ports. The initial pin states, before pin configurations, are configured elegantly to avoid some problems.
9-1
I/O PORTS
S3C2400 RISC MICROPROCESSOR
Table 9-1. S3C2400 Port Configuration Overview Port A PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 output only output only output only output only output only output only output only output only output only output only output only output only output only output only output only output only output only output only Selectable Pin Functions nGCS[5] nGCS[4] nGCS[3] nGCS[2] nGCS[1] nCAS[1] nCAS[0] SCKE A24 A23 A22 A21 A20 A19 A18 A17 A16 A0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9-2
S3C2400 RISC MICROPROCESSOR
I/O PORTS
Table 9-1. S3C2400 Port Configuration Overview (Continued) Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin Functions DATA31 DATA30 DATA29 DATA28 DATA27 DATA26 DATA25 DATA24 DATA23 DATA22 DATA21 DATA20 DATA19 DATA18 DATA17 DATA16 - - - - - nSS I2SSDI - - nRTS[1] nCTS[1] RXD[1] TXD[1] TCLK[1] nXBREQ nXBACK - - - - - - - - - - - - - - - -
9-3
I/O PORTS
S3C2400 RISC MICROPROCESSOR
Table 9-1. S3C2400 Port Configuration Overview (Continued) Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin Functions VD[15] VD[14] VD[13] VD[12] VD[11] VD[10] VD[9] VD[8] VD[7] VD[6] VD[5] VD[4] VD[3] VD[2] VD[1] VD[0] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Port D PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output
Selectable Pin Functions nWAIT TCLK[0] TOUT[3] TOUT[2] TOUT[1] TOUT[0] LEND VCLK VLINE VM VFRAME - - - - - - I2SSDI - - - - - - - - - - - - - - -
9-4
S3C2400 RISC MICROPROCESSOR
I/O PORTS
Table 9-1. S3C2400 Port Configuration Overview (Continued) Port E PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin Functions nXDREQ[1] nXDREQ[0] nXDACK[1] nXDACK[0] EINT[7] EINT[6] EINT[5] EINT[4] EINT[3] EINT[2] EINT[1] EINT[0] nXBREQ - nXBACK - - - TCLK[1] nRTS[1] nCTS[1] I2SSDI nSS - - - - - - - - - - - - -
Port F PF6 PF5 PF4 PF3 PF2 PF1 PF0 input/output input/output input/output input/output input/output input/output input/output
Selectable Pin Functions CLKOUT nCTS[0] nRTS[0] TXD[1] TXD[0] RXD[1] RXD[0] - nXBREQ nXBACK IICSCL - IICSDA - - - - - - - -
Port G PG9 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0
NOTE:
Selectable Pin Functions input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output SPICLK SPIMOSI SPIMISO MMCDAT MMCCMD MMCCLK I2SSDO CDCLK I2SSCLK I2SLRCK MMCCLK IICSCL IICSDA IICSCL IICSDA I2SSDI I2SSDI - - - - - - - - - - - - -
The underlined function name is selected just after a reset.
9-5
I/O PORTS
S3C2400 RISC MICROPROCESSOR
9-6
S3C2400 RISC MICROPROCESSOR
I/O PORTS
PORT CONTROL DESCRIPTIONS
PORT CONFIGURATION REGISTER (PACON-PGCON) In S3C2400, most pins are multiplexed pins. So, It is determined which function is selected for each pins. The PnCON (port control register) determines which function is used for each pin. If PE0 - PE7 is used for the wakeup signal in power down mode, these ports must be configured in interrupt mode.
PORT DATA REGISTER (PADAT-PGDAT) If Ports are configured as output ports, data can be written to the corresponding bit of PnDAT. If Ports are configured as input ports, the data can be read from the corresponding bit of PnDAT.
PORT PULL-UP REGISTER (PBUP-PGUP) The port pull-up register controls the pull-up resister enable/disable of each port group. When the corresponding bit is 0, the pull-up resister of the pin is enabled. When 1, the pull-up resister is disabled. If the port pull-up register is enabled then the pull-up resisters work without pin's functional setting(input, output, DATAn, EINTn and etc)
OPEN DRAIN CONTROL REGISTER The port open drain control register controls the open drain function enable/disable of 6 pad of 2 port group. When the corresponding bit is 1, the open drain function of the pin is enabled. When 0, the open drain function is disabled.
MISCELLANEOUS CONTROL REGISTER This register controls lower two byte DATA port pull-up resister, hi-z state or previous state in stop mode, USB pad, and CLKOUT selection.
EXTERNAL INTERRUPT CONTROL REGISTER The 8 external interrupts are requested by various signaling methods. The EXTINT register configures the signaling method among the low level trigger, high level trigger, falling edge trigger, rising edge trigger, and both edge trigger for the external interrupt request Because each external interrupt pin has a digital filter, the interrupt controller can recognize the request signal that is longer than 3 clocks.
9-7
I/O PORTS
S3C2400 RISC MICROPROCESSOR
I/O PORT CONTROL REGISTER
PORT A CONTROL REGISTERS (PACON, PADAT) Register PACON PADAT Address 0x15600000 0x15600004 R/W R/W R/W Description Configures the pins of port A The data register for port A Reset Value 0x3ffff Undef.
PACON PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17
Bit [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output
Description 1 = ADDR0 1 = ADDR16 1 = ADDR17 1 = ADDR18 1 = ADDR19 1 = ADDR20 1 = ADDR21 1 = ADDR22 1 = ADDR23 1 = ADDR24 1 = SCKE 1 = nCAS[0] 1 = nCAS[1] 1 = nGCS[1] 1 = nGCS[2] 1 = nGCS[3] 1 = nGCS[4] 1 = nGCS[5]
PADAT PA[17:0]
Bit [17:0]
Description When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
9-8
S3C2400 RISC MICROPROCESSOR
I/O PORTS
PORT B CONTROL REGISTERS (PBCON, PBDAT, PBUP) Register PBCON PBDAT PBUP Address 0x15600008 0x1560000C 0x15600010 R/W R/W R/W R/W Description Configures the pins of port B The data register for port B pull-up disable register for port B Reset Value 0xaaaaaaaa Undef. 0x0
PBCON PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15
Bit [1:0] [3:2] [5:4] [7:6] [9:8] [11:10] [13:12] [15:14] [17:16] [19:18] [21:20] [23:22] [25:24] [27:26] [29:28] [31:30] 00 = Input 10 = DATA16 00 = Input 10 = DATA17 00 = Input 10 = DATA18 00 = Input 10 = DATA19 00 = Input 10 = DATA20 00 = Input 10 = DATA21 00 = Input 10 = DATA22 00 = Input 10 = DATA23 00 = Input 10 = DATA24 00 = Input 10 = DATA25 00 = Input 10 = DATA26 00 = Input 10 = DATA27 00 = Input 10 = DATA28 00 = Input 10 = DATA29 00 = Input 10 = DATA30 00 = Input 10 = DATA31
Description 01 = Output 11 = nXBACK 01 = Output 11 = nXBREQ 01 = Output 11 = TCLK[1] 01 = Output 11 = TXD[1] 01 = Output 11 = RXD[1] 01 = Output 11 = nCTS[1] 01 = Output 11 = nRTS[1] 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = I2SSDI 01 = Output 11 = nSS 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved
9-9
S3C2400 RISC MICROPROCESSOR
I/O PORTS
PBDAT PB[15:0]
Bit [15:0]
Description When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
PBUP PB[15:0]
Bit [15:0]
Description 0 = the pull up function attached to to the corresponding port pin is enabled. 1 = the pull up function is disabled.
9-10
S3C2400 RISC MICROPROCESSOR
I/O PORTS
PORT C CONTROL REGISTERS (PCCON, PCDAT, PCUP) Register PCCON PCDAT PCUP Address 0x15600014 0x15600018 0x1560001C R/W R/W R/W R/W Description Configures the pins of port C The data register for port C pull-up disable register for port C Reset Value 0x0 Undef. 0x0
PCCON PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15
Bit [1:0] [3:2] [5:4] [7:6] [9:8] [11:10] [13:12] [15:14] [17:16] [19:18] [21:20] [23:22] [25:24] [27:26] [29:28] [31:30] 00 = Input 10 = VD[0] 00 = Input 10 = VD[1] 00 = Input 10 = VD[2] 00 = Input 10 = VD[3] 00 = Input 10 = VD[4] 00 = Input 10 = VD[5] 00 = Input 10 = VD[6] 00 = Input 10 = VD[7] 00 = Input 10 = VD[8] 00 = Input 10 = VD[9] 00 = Input 10 = VD[10] 00 = Input 10 = VD[11] 00 = Input 10 = VD[12] 00 = Input 10 = VD[13] 00 = Input 10 = VD[14] 00 = Input 10 = VD[15]
Description 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved
9-11
S3C2400 RISC MICROPROCESSOR
I/O PORTS
PCDAT PC[15:0]
Bit [15:0]
Description When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
PCUP PC[15:0]
Bit [15:0]
Description 0 = the pull up function attached to the corresponding port pin is enabled. 1 = the pull up function is disabled.
9-12
S3C2400 RISC MICROPROCESSOR
I/O PORTS
PORT D CONTROL REGISTERS (PDCON, PDDAT, PDUP) Register PDCON PDDAT PDUP Address 0x15600020 0x15600024 0x15600028 R/W R/W R/W R/W Description Configures the pins of port D The data register for port D pull-up disable register for port D Reset Value 0x0 Undef. 0x620
PDCON PD0 PD1 PD2 PD3 PD4 PD5 (note) PD6 PD7 PD8 PD9 (note) PD10 (note)
NOTE:
Bit [1:0] [3:2] [5:4] [7:6] [9:8] [11:10] [13:12] [15:14] [17:16] [19:18] [21:20] 00 = Input 10 = VFRAME 00 = Input 10 = VM 00 = Input 10 = VLINE 00 = Input 10 = VCLK 00 = Input 10 = LEND 00 = Input 10 = TOUT[0] 00 = Input 10 = TOUT[1] 00 = Input 10 = TOUT[2] 00 = Input 10 = TOUT[3] 00 = Input 10 = TCLK[0] 00 = Input 10 = nWAIT
Description 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = I2SSDI 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved
pd5, pd9, pd10 are `pull-up disable' state at the initial condition.
PDDAT PD[10:0]
Bit [10:0]
Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as a functional pin, the undefined value will be read.
PDUP PD[10:0]
Bit [10:0]
Description 0 = the pull up function attached to to the corresponding port pin is enabled. 1 = the pull up function is disabled.
9-13
I/O PORTS
S3C2400 RISC MICROPROCESSOR
PORT E CONTROL REGISTERS (PECON, PEDAT) If PE0 - PE7 will be used for wake-up signals at power down mode, the ports will be set in interrupt mode. Register PECON PEDAT PEUP Address 0x1560002C 0x15600030 0x15600034 R/W R/W R/W R/W Description Configures the pins of port E The data register for port E pull-up disable register for port E Reset Value 0x0 Undef. 0x003
PECON *PE0 *PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11
NOTE:
Bit [1:0] [3:2] [5:4] [7:6] [9:8] [11:10] [13:12] [15:14] [17:16] [19:18] [21:20] [23:22] 00 = Input 10 = EINT[0] 00 = Input 10 = EINT[1] 00 = Input 10 = EINT2] 00 = Input 10 = EINT[3] 00 = Input 10 = EINT[4] 00 = Input 10 = EINT[5] 00 = Input 10 = EINT[6] 00 = Input 10 = EINT[7] 00 = Input 10 = nXDACK[0] 00 = Input 10 = nXDACK[1] 00 = Input 10 = nXDREQ[0] 00 = Input 10 = nXDREQ[1]
Description 01 = Output 11 = Reserved 01 = Output 11 = nSS 01 = Output 11 = I2SSDI 01 = Output 11 = nCTS[1] 01 = Output 11 = nRTS[1] 01 = Output 11 = TCLK[1] 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = nXBACK 01 = Output 11 = Reserved 01 = Output 11 = nXBREQ
* pd0, pd1 are `pull-up disable' state at the initial condition.
9-14
S3C2400 RISC MICROPROCESSOR
I/O PORTS
PEDAT PE[11:0]
Bit [11:0]
Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
PEUP PE[11:0]
Bit [11:0]
Description 0 = the pull up function attached to to the corresponding port pin is enabled. 1 = the pull up function is disabled.
9-15
I/O PORTS
S3C2400 RISC MICROPROCESSOR
PORT F CONTROL REGISTERS (PFCON, PFDAT, PFUP) Register PFCON PFDAT PFUP Address 0x15600038 0x1560003C 0x15600040 R/W R/W R/W R/W Description Configures the pins of port F The data register for port F Pull-up disable register for port F Reset Value 0x0 Undef. 0x0
PFCON PF0 PF1 PF2 PF3 PF4 PF5 PF6
Bit [1:0] [3:2] [5:4] [7:6] [9:8] [11:10] [13:12] 00 = Input 10 = RXD[0] 00 = Input 10 = RXD[1] 00 = Input 10 = TXD[0] 00 = Input 10 = TXD[1] 00 = Input 10 = nRTS[0] 00 = Input 10 = nCTS[0] 00 = Input 10 = CLKOUT
Description 01 = Output 11 = Reserved 01 = Output 11 = IICSDA 01 = Output 11 = Reserved 01 = Output 11 = IICSCL 01 = Output 11 = nXBACK 01 = Output 11 = nXBREQ 01 = Output 11 = Reserved
PFDAT PF[6:0]
Bit [6:0]
Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
PFUP PF[6:0]
Bit [6:0]
Description 0 = the pull up function attached to to the corresponding port pin is enabled. 1 = the pull up function is disabled.
9-16
S3C2400 RISC MICROPROCESSOR
I/O PORTS
PORT G CONTROL REGISTERS (PGCON, PGDAT, PGUP) Register PGCON PGDAT PGUP Address 0x15600044 0x15600048 0x1560004C R/W R/W R/W R/W Description Configures the pins of port G The data register for port G Pull-up disable register for port G Reset Value 0x0 Undef. 0x0
PGCON PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9
Bit [1:0] [3:2] [5:4] [7:6] [9:8] [11:10] [13:12] [15:14] [17:16] [19:18] 00 = Input 10 = I2SLRCK 00 = Input 10 = I2SSCLK 00 = Input 10 = CDCLK 00 = Input 10 = I2SSDO 00 = Input 10 = MMCCLK 00 = Input 10 = MMCCMD 00 = Input 10 = MMCDAT 00 = Input 10 = SPIMISO 00 = Input 10 = SPIMOSI 00 = Input 10 = SPICLK
Description 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = I2SSDI 01 = Output 11 = I2SSDI 01 = Output 11 = IICSDA 01 = Output 11 = IICSCL 01 = Output 11 = IICSDA 01 = Output 11 = IICSCL 01 = Output 11 = MMCCLK
PGDAT PG[9:0]
Bit [9:0]
Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as a functional pin, the undefined value will be read.
PGUP PG[9:0]
Bit [9:0]
Description 0 = the pull up function attached to to the corresponding port pin is enabled. 1 = the pull up function is disabled.
9-17
I/O PORTS
S3C2400 RISC MICROPROCESSOR
OPEN DRAIN CONTROL REGISTER (OPENCR) Port F[1], F[3] and Port G[8:5] pin's open drain mode can be controlled by OPENCR register. Register OPENCR Address 0x15600050 R/W R/W Description Open-drain enable register Reset Value 0x0
OPENCR OPC_RXD1 OPC_TXD1 OPC_CMD OPC_DAT OPC_MISO OPC_MOSI
Bit [0] [1] [2] [3] [4] [5]
Description 0 = PF[1] port open-drain mode is disabled 1 = PF[1] port open-drain mode is enabled 0 = PF[3] port open-drain mode is disabled 1 = PF[3] port open-drain mode is enabled 0 = PG[5] port open-drain mode is disabled 1 = PG[5] port open-drain mode is enabled 0 = PG[6] port open-drain mode is disabled 1 = PG[6] port open-drain mode is enabled 0 = PG[7] port open-drain mode is disabled 1 = PG[7] port open-drain mode is enabled 0 = PG[8] port open-drain mode is disabled 1 = PG[8] port open-drain mode is enabled
9-18
S3C2400 RISC MICROPROCESSOR
I/O PORTS
MISCELLANEOUS Control Register (MISCCR) D[15:0] pin pull-up resister can be controlled by MISCCR register. In STOP mode, the data bus(D[31:0] or D[15:0] is Hi-Z state. But, because of the characteristics of IO pad, the data bus pull-up resisters have to be turned on to reduce the power consumption in STOP mode. D[31:16] pin pull-up resisters can be controlled by PBUP register. D[15:0] pin pull-up resisters can be controlled by MISCCR register. In STOP mode, memory control signals (A[24:0], nGCS[5:0], nWE, nOE, nBE:nWBE:DQM) can be selectable Hi-z state or previous state in order to protect memory mal-function by setting the Error! Bookmark not defined. field in MISCCR register. Pads related USB are controlled by this register for USB host, or for USB device. CLKOUT signal can be selectable FCLK, HCLK, PCLK, MPLL CLK, or UPLL CLK by setting the CLKSEL field. Because of the pad delay, CLKOUT signal doesn't have same phase with it's original clock source(Internal FCLK, HCLK, PCLK, MPLL CLK, and UPLL CLK) Register MISCCR Address 0x15600054 R/W R/W Description Miscellaneous control register Reset Value 0x00
MISCCR SPUCR0 SPUCR1 HZ@STOP USBPAD CLKSEL
Bit [0] [1] [2] [3] [6:4]
Description 0 = DATA[7:0] port pull-up resister is enabled 1 = DATA[7:0] port pull-up resister is disabled 0 = DATA[15:8] port pull-up resister is enabled 1 = DATA[15:8] port pull-up resister is disabled 0 = HZ @ stop 1 = Previous state of PAD.
0 = use pads related USB for USB device 1 = use pads related USB for USB host 000 = Select MPLL CLK with CLKOUT pad 001 = Select UPLL CLK with CLKOUT pad 010 = Select FCLK with CLKOUT pad 011 = Select HCLK with CLKOUT pad 1xx = Select PCLK with CLKOUT pad
NOTE: CLKOUT is prepared to monitor an internal clock situation (On/Off status or frequency).
9-19
I/O PORTS
S3C2400 RISC MICROPROCESSOR
EXTINT (EXTERNAL INTERRUPT CONTROL REGISTER) The 8 external interrupts can be requested by various signaling methods. The EXTINT register configures the signaling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity. To recognize the level interrupt, the valid logic level on EXTINTn pin must be retained for 40ns at least because of the noise filter. Register EXTINT Address 0x15600058 R/W R/W Description External Interrupt control Register Reset Value 0x000000
EXTINT EINT0
Bit [2:0]
Description Setting the signaling method of the EINT0. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT1. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT2. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT3. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT4. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT5. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT6. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT7. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered
EINT1
[6:4]
EINT2
[10:8]
EINT3
[14:12]
EINT4
[18:16]
EINT5
[22:20]
EINT6
[26:24]
EINT7
[30:28]
9-20
S3C2400 RISC MICROPROCESSOR
I/O PORTS
NOTES
9-21
S3C2400 RISC MICROPROCESSOR
PWM TIMER
10
OVERVIEW
PWM TIMER
The S3C2400 has five 16-bit timers. The timer 0, 1, 2, 3 have PWM function (Pulse Width Modulation). Timer 4 has an internal timer only with no output pins. Timer 0 has a dead-zone generator, which is used with a large current device. Timer 0 and timer 1 share an 8-bit prescaler, timers 2 & 3 share the other 8-bit prescaler. Each timer has a clockdivider which has 5 different divided signals (1/2, 1/4, 1/8, 1/16, TCLK). Each timer block receives its own clock signals from the clock-divider, which receives the clock from the corresponding 8-bit prescaler. The 8-bit prescaler is programmable and divides the MUX output signal (PHCLK) according to the loading value which is stored in TCFG0 and TCFG1 registers. The timer count buffer register (TCNTBn) has an initial value which is loaded into the down-counter when the timer is enabled. The timer compare buffer register (TCMPBn) has an initial value which is loaded into the compare register to be compared with the down-counter value. This double buffering feature of TCNTBn and TCMPBn makes the timer generate a stable output when the frequency and duty ratio are changed. Each timer has its own 16-bit down-counter which is driven by the timer clock. When the down-counter reaches zero, the timer interrupt request is generated to inform the CPU that the timer operation has been completed. When the timer counter reaches zero, the value of corresponding TCNTBn is automatically loaded into the down-counter to continue the next operation. However, if the timer stops, for example, by clearing the timer enable bit of TCONn during the timer running mode, the value of TCNTBn will not be reloaded into the counter. The value of TCMPBn is used for PWM (pulse width modulation). The timer control logic changes the output level when the down-counter value matches the value of the compare register in the timer control logic. Therefore, the compare register determines the turn-on time (or turn-off time) of an PWM output.
FEATURES -- Five 16-bit timers -- Two 8-bit prescalers & Five 4-bit divider -- Programmable duty control of output waveform (PWM) -- Auto-reload mode or one-shot pulse mode -- Dead-zone generator
10-1
PWM TIMER
S3C2400 RISC MICROPROCESSOR
TCMPB0
TCNTB0 Dead Zone Generator Control Logic0
TOUT0
5:1 MUX
Dead Zone
PCLK 8-Bit Prescaler
1/2 1/4 1/8 1/16 TCLK0 Clock Divider 5:1 MUX TCMPB2 5:1 MUX TCMPB1 TCNTB1 TOUT1 Control Logic1
Dead Zone
TCNTB2
TOUT2 Control Logic2
1/2 1/4 8-Bit Prescaler 1/8 1/16 TCLK1 Clock Divider TOUT3 Control Logic3 5:1 MUX 5:1 MUX TCMPB3 TCNTB3
TCNTB4
Control Logic4
No Pin
Figure 10-1. 16-bit PWM Timer Block Diagram
10-2
S3C2400 RISC MICROPROCESSOR
PWM TIMER
PWM TIMER OPERATION
PRESCALER & DIVIDER An 8-bit prescaler and 4-bit divider make the following output frequencies: 4-bit Divider Settings 1/2 (PCLK = 66 MHz) 1/4 (PCLK = 66 MHz) 1/8 (PCLK = 66 MHz) 1/16 (PCLK = 66 MHz) Minimum Resolution (Prescaler = 0) 0.0303 us (33.0000 MHz) 0.0606 us (16.5000 MHz) 0.1212 us (8.2500 MHz) 0.2424 us (4.1250 MHz) Maximum Resolution (Prescaler = 255) 7.7575 us (128.9063 KHz) 15.5151 us (64.4531 KHz) 31.0303 us (32.2266 KHz) 62.0606 us (16.1133 KHz) Maximum Interval (TCNTBn = 65535) 0.5084 sec 1.0168 sec 2.0336 sec 4.0671 sec
BASIC TIMER OPERATION
Start bit=1
Timer is started TCNTn=TCMPn
Auto-reload
TCNTn=TCMPn
Timer is stopped
TCMPn
1
0
TCNTn
3
3
2
1
0
2
1
0
0
TCNTBn=3 TCNTBn=1 Manual update=1 Auto-reload=1
TCNTBn=2 TCNTBn=0 Manual update=0 Auto-reload=1
Auto-reload Interrupt request Interrupt request
TOUTn
Command Status
Figure 10-2. Timer Operations A timer (except the timer ch-5) has TCNTBn, TCNTn, TCMPBn and TCMPn. TCNTBn and TCMPBn are loaded into TCNTn and TCMPn when the timer reaches 0. When TCNTn reaches 0, the interrupt request will occur if the interrupt is enabled. (TCNTn and TCMPn are the names of the internal registers. The TCNTn register can be read from the TCNTOn register)
10-3
PWM TIMER
S3C2400 RISC MICROPROCESSOR
AUTO-RELOAD & DOUBLE BUFFERING S3C2400 PWM Timers have a double buffering feature, which can change the reload value for the next timer operation without stopping the current timer operation. So, although the new timer value is set, a current timer operation is completed successfully. The timer value can be written into TCNTBn (Timer Count Buffer register) and the current counter value of the timer can be read from TCNTOn (Timer Count Observation register). If TCNTBn is read, the read value is not the current state of the counter but the reload value for the next timer duration. The auto-reload is the operation, which copies the TCNTBn into TCNTn when TCNTn reaches 0. The value, written into TCNTBn, is loaded to TCNTn only when the TCNTn reaches to 0 and auto-reload is enabled. If the TCNTn is 0 and the auto-reload bit is 0, the TCNTn does not operate any further.
Write TCNTBn = 100 Start TCNTBn = 150
Write TCNTBn = 200
Auto-reload 150 100 100 200
Interrupt
Figure 10-3. Example of Double Buffering Feature
10-4
S3C2400 RISC MICROPROCESSOR
PWM TIMER
TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT Because an auto-reload operation of the timer occurs when the down counter reaches to 0, a starting value of the TCNTn has to be defined by the user at first. In this case, the starting value has to be loaded by the manual update bit. The sequence of starting a timer is as follows; 1) Write the initial value into TCNTBn and TCMPBn 2) Set the manual update bit of the corresponding timer. It is recommended to configure the inverter on/off bit. (whether use inverter or not) 3) Set start bit of corresponding timer to start the timer(At the same time, clear the manual update bit). Also, if the timer is stopped by force, the TCNTn retains the counter value and is not reloaded from TCNTBn. If new value has to be set, manual update has to be done. NOTE Whenever TOUT inverter on/off bit is changed, the TOUTn logic value will be changed whether or not the timer runs. Therefore, it is desirable that the inverter on/off bit is configured with the manual update bit.
10-5
PWM TIMER
S3C2400 RISC MICROPROCESSOR
EXAMPLE OF A TIMER OPERATION
1
2
3
4
6
79
10
TOUTn
50
110
40
40 20
60
5
8
11
Figure 10-4. Example of a Timer Operation The result of the following procedure is shown in Figure10-4; 1. Enable the auto-reload feature. Set the TCNTBn as 160 (50+110) and the TCMPBn as 110. Set the manual update bit and configure the inverter bit(on/off). The manual update bit sets TCNTn and TCMPn to the values of TCNTBn and TCMPBn, respectively. And then, set TCNTBn and TCMPBn as 80 (40+40) and 40, respectively, to determine the next reload value. 2. 3. 4. 5. 6. 7. 8. 9. Set the start bit, provided that manual_update is 0 and inverter is off and auto-reload is on. The timer starts counting down after latency time within the timer resolution. When TCNTn has the same value with TCMPn, the logic level of TOUTn is changed from low to high. When TCNTn reaches 0, the interrupt request is generated and TCNTBn value is loaded into a temporary register. At the next timer tick, TCNTn is reloaded with the temporary register value(TCNTBn). In the ISR(Interrupt Service Routine), the TCNTBn and TCMPBn are set as 80 (20+60) and 60, respectively, which is used for the next duration. When TCNTn has the same value as TCMPn, the logic level of TOUTn is changed from low to high. When TCNTn reaches 0, TCNTn is reloaded automatically with TCNTBn. At the same time, the interrupt request is generated. In the ISR (Interrupt Service Routine), auto-reload and interrupt request are disabled to stop the timer. When the value of TCNTn is same as TCMPn, the logic level of TOUTn is changed from low to high.
10. Even when TCNTn reaches to 0, TCNTn is not any more reloaded and the timer is stopped because auto-reload has been disabled. 11. No interrupt request is generated.
10-6
S3C2400 RISC MICROPROCESSOR
PWM TIMER
PWM (PULSE WIDTH MODULATION)
60
50
40
30
30
Write TCMPBn = 60 Write TCMPBn = 50
Write TCMPBn = 40 Write TCMPBn = 30
Write TCMPBn = 30 Write TCMPBn = Next PWM Value
Figure 10-5. Example of PWM PWM feature can be implemented by using the TCMPBn. PWM frequency is determined by TCNTBn. A PWM value is determined by TCMPBn in figure 10-5. For a higher PWM value, decrease the TCMPBn value. For a lower PWM value, increase the TCMPBn value. If an output inverter is enabled, the increment/decrement may be reversed. Because of the double buffering feature, TCMPBn, for a next PWM cycle, can be written at any point in the current PWM cycle by ISR or something else
10-7
PWM TIMER
S3C2400 RISC MICROPROCESSOR
OUTPUT LEVEL CONTROL
Inverter off
Inverter on Initial State Period 1 Period 2 Timer Stop
Figure 10-6. Inverter On/Off The following methods can be used to maintain TOUT as high or low.(assume the inverter is off) 1. 2. 3. Turn off the auto-reload bit. And then, TOUTn goes to high level and the timer is stopped after TCNTn reaches to 0. This method is recommended. Stop the timer by clearing the timer start/stop bit to 0. If TCNTn TCMPn, the output level is high. If TCNTn >TCMPn, the output level is low. TOUTn can be inverted by the inverter on/off bit in TCON. The inverter removes the additional circuit to adjust the output level.
10-8
S3C2400 RISC MICROPROCESSOR
PWM TIMER
DEAD ZONE GENERATOR The dead zone is for the PWM control in a power device. This feature is used to insert the time gap between a turnoff of a switching device and a turn on of another switching device. This time gap prohibits the two switching devices turning on simultaneously, even for a very short time. TOUT0 is the PWM output. nTOUT0 is the inversion of the TOUT0. If the dead zone is enabled, the output wave form of TOUT0 and nTOUT0 will be TOUT0_DZ and nTOUT0_DZ, respectively. nTOUT0_DZ is routed to the TOUT1 pin. In the dead zone interval, TOUT0_DZ and nTOUT0_DZ can never be turned on simultaneously.
TOUT0
nTOUT0
Deadzone Interval
TOUT0_DZ
nTOUT0_DZ
Figure 10-7. The Wave Form When a Dead Zone Feature is Enabled
10-9
PWM TIMER
S3C2400 RISC MICROPROCESSOR
DMA REQUEST MODE The PWM timer can generate a DMA request at every specific times. The timer keeps DMA request signal (nDMA_REQ) low until the timer receives the ACK signal. When the timer receives the ACK signal, it makes the request signal inactive. The timer, which generates the DMA request, is determined by setting DMA mode bits(in TCFG1 register). If one of timers is configured as DMA request mode, that timer does not generate an interrupt request. The others can generate interrupt normally. DMA mode configuration and DMA / interrupt operation DMA mode 0000 0001 0010 0011 0100 0101 0110 DMA request No select Timer0 Timer1 Timer2 Timer3 Timer4 No select Timer0 INT ON OFF ON ON ON ON ON Timer1 INT ON ON OFF ON ON ON ON Timer2 INT ON ON ON OFF ON ON ON Timer3 INT ON ON ON ON OFF ON ON Timer4 INT ON ON ON ON ON OFF ON
PCLK
INT4tmp
DMAreq_en
101
nDMA_ACK
nDMA_REQ
INT4
Figure 10-8. The Timer 4 DMA Mode Operation
10-10
S3C2400 RISC MICROPROCESSOR
PWM TIMER
PWM TIMER CONTROL REGISTERS
TIMER CONFIGURATION REGISTER0 (TCFG0) Timer input clock Frequency = PCLK / {prescaler value+1} / {divider value} {prescaler value} = 0-255 {divider value} = 2, 4, 8, 16,TCLKn Register TCFG0 Address 0x15100000 R/W R/W Description Configures the two 8-bit prescalers Reset Value 0x00000000
TCFG0 Reserved Dead zone length Prescaler 1 Prescaler 0
Bit [31:24] [23:16] [15:8] [7:0]
Description
Initial State 0x00
These 8 bits determine the dead zone length. The 1 unit time of the dead zone length is equal to the 1 unit time of timer 0. These 8 bits determine prescaler value for Timer 2, 3 and 4 These 8 bits determine prescaler value for Timer 0 and 1
0x00 0x00 0x00
10-11
PWM TIMER
S3C2400 RISC MICROPROCESSOR
TIMER CONFIGURATION REGISTER1 (TCFG1) Register TCFG1 Address 0x15100004 R/W R/W Description 5-MUX & DMA mode selecton register Reset Value 0x00000000
TCFG1 Reserved DMA mode
Bit [31:24] [23:20]
Description
Initial State 00000000
Select DMA request channel 0000 = No select (All interrupt) 0001 = Timer0 0010 = Timer1 0011 = Timer2 0100 = Timer3 0101 = Timer4 0110 = Reserved Select MUX input for PWM Timer4. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK1 Select MUX input for PWM Timer3. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK1 Select MUX input for PWM Timer2. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK1 Select MUX input for PWM Timer1. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK0 Select MUX input for PWM Timer0. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK0
0000
MUX 4
[19:16]
0000
MUX 3
[15:12]
0000
MUX 2
[11:8]
0000
MUX 1
[7:4]
0000
MUX 0
[3:0]
0000
10-12
S3C2400 RISC MICROPROCESSOR
PWM TIMER
TIMER CONTROL REGISTER (TCON) Register TCON Address 0x15100008 R/W R/W Description Timer control register Reset Value 0x00000000
TCON Timer 4 auto reload on/off Timer 4 manual update (note) Timer 4 start/stop Timer 3 auto reload on/off Timer 3 output inverter on/off Timer 3 manual update (note) Timer 3 start/stop Timer 2 auto reload on/off Timer 2 output inverter on/off Timer 2 manual update (note) Timer 2 start/stop Timer 1 auto reload on/off Timer 1 output inverter on/off Timer 1 manual update (note) Timer 1 start/stop
NOTE:
Bit [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8]
Description This bit determines auto reload on/off for Timer 4. 0 = One-shot 1 = Interval mode (auto reload) This bit determines the manual update for Timer 4. 0 = No operation 1 = Update TCNTB4 This bit determines start/stop for Timer 4. 0 = Stop 1 = Start for Timer 4 This bit determines auto reload on/off for Timer 3. 0 = One-shot 1 = Interval mode (auto reload) This bit determines output inverter on/off for Timer 3. 0 = Inverter off 1 = Inverter on for TOUT3 This bit determine manual update for Timer 3. 0 = No operation 1 = Update TCNTB3, TCMPB3 This bit determines start/stop for Timer 3. 0 = Stop 1 = Start for Timer 3 This bit determines auto reload on/off for Timer 2. 0 = One-shot 1 = Interval mode (auto reload) This bit determines output inverter on/off for Timer 2. 0 = Inverter off 1 = Inverter on for TOUT2 This bit determines the manual update for Timer 2. 0 = No operation 1 = Update TCNTB2, TCMPB2 This bit determines start/stop for Timer 2. 0 = Stop 1 = Start for Timer 2 This bit determines the auto reload on/off for Timer1. 0 = One-shot 1 = Interval mode (auto reload) This bit determines the output inverter on/off for Timer1. 0 = Inverter off 1 = Inverter on for TOUT1 This bit determines the manual update for Timer 1. 0 = No operation 1 = Update TCNTB1, TCMPB1 This bit determines start/stop for Timer 1. 0 = Stop 1 = Start for Timer 1
initial state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This bit has to be cleared at next writing.
10-13
S3C2400 RISC MICROPROCESSOR
PWM TIMER
TCON Dead zone enable Timer 0 auto reload on/off Timer 0 output inverter on/off Timer 0 manual update (note) Timer 0 start/stop
NOTE:
Bit [4] [3] [2] [1] [0]
Description This bit determines the dead zone operation. 0 = Disable 1 = Enable This bit determines auto reload on/off for Timer 0. 0 = One-shot 1 = Interval mode(auto reload) This bit determines the output inverter on/off for Timer 0. 0 = Inverter off 1 = Inverter on for TOUT0 This bit determines the manual update for Timer 0. 0 = No operation 1 = Update TCNTB0, TCMPB0 This bit determines start/stop for Timer 0. 0 = Stop 1 = Start for Timer 0
initial state 0 0 0 0 0
This bit has to be cleared at next writing.
10-14
S3C2400 RISC MICROPROCESSOR
PWM TIMER
TIMER 0 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB0, TCMPB0) Register TCNTB0 TCMPB0 Address 0x1510000C 0x15100010 R/W R/W R/W Description Timer 0 count buffer register Timer 0 compare buffer register Reset Value 0x00000000 0x00000000
TCMPB0 Timer 0 compare buffer register
Bit [15:0]
Description Setting compare buffer value for Timer 0
Initial State 0x00000000
TCNTB0 Timer 0 count buffer register
Bit [15:0]
Description Setting count buffer value for Timer 0
Initial State 0x00000000
TIMER 0 COUNT OBSERVATION REGISTER (TCNTO0) Register TCNTO0 Address 0x15100014 R/W R Description Timer 0 count observation register Reset Value 0x00000000
TCNTO0 Timer 0 observation register
Bit [15:0]
Description Setting count observation value for Timer 0
Initial State 0x00000000
10-15
PWM TIMER
S3C2400 RISC MICROPROCESSOR
TIMER 1 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB1, TCMPB1) Register TCNTB1 TCMPB1 Address 0x15100018 0x1510001C R/W R/W R/W Description Timer 1 count buffer register Timer 1 campare buffer register Reset Value 0x00000000 0x00000000
TCMPB1 Timer 1 compare buffer register
Bit [15:0]
Description Setting compare buffer value for Timer 1
Initial State 0x00000000
TCNTB1 Timer 1 count buffer register
Bit [15:0]
Description Setting count buffer value for Timer 1
Initial State 0x00000000
TIMER 1 COUNT OBSERVATION REGISTER (TCNTO1) Register TCNTO1 Address 0x15100020 R/W R Description Timer 1 count observation register Reset Value 0x00000000
TCNTO1 Timer 1 observation register
Bit [15:0]
Description Setting count observation value for Timer 1
initial state 0x00000000
10-16
S3C2400 RISC MICROPROCESSOR
PWM TIMER
TIMER 2 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB2, TCMPB2) Register TCNTB2 TCMPB2 Address 0x15100024 0x15100028 R/W R/W R/W Description Timer 2 count buffer register Timer 2 campare buffer register Reset Value 0x00000000 0x00000000
TCMPB2 Timer 2 compare buffer register
Bit [15:0]
Description Setting compare buffer value for Timer 2
Initial State 0x00000000
TCNTB2 Timer 2 count buffer register
Bit [15:0]
Description Setting count buffer value for Timer 2
Initial State 0x00000000
TIMER 2 COUNT OBSERVATION REGISTER (TCNTO2) Register TCNTO2 Address 0x1510002C R/W R Description Timer 2 count observation register Reset Value 0x00000000
TCNTO2 Timer 2 observation register
Bit [15:0]
Description Setting count observation value for Timer 2
Initial State 0x00000000
10-17
PWM TIMER
S3C2400 RISC MICROPROCESSOR
TIMER 3 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB3, TCMPB3) Register TCNTB3 TCMPB3 Address 0x15100030 0x15100034 R/W R/W R/W Description Timer 3 count buffer register Timer 3 campare buffer register Reset Value 0x00000000 0x00000000
TCMPB3 Timer 3 compare buffer register
Bit [15:0]
Description Setting compare buffer value for Timer 3
Initial State 0x00000000
TCNTB3 Timer 3 count buffer register
Bit [15:0]
Description Setting count buffer value for Timer 3
Initial State 0x00000000
TIMER 3 COUNT OBSERVATION REGISTER (TCNTO3) Register TCNTO3 Address 0x15100038 R/W R Description Timer 3 count observation register Reset Value 0x00000000
TCNTO3 Timer 3 observation register
Bit [15:0]
Description Setting count observation value for Timer 3
Initial State 0x00000000
10-18
S3C2400 RISC MICROPROCESSOR
PWM TIMER
TIMER 4 COUNT BUFFER REGISTER (TCNTB4) Register TCNTB4 Address 0x1510003C R/W R/W Description Timer 4 count buffer register Reset Value 0x00000000
TCNTB4 Timer 4 count buffer register
Bit [15:0]
Description Setting count buffer value for Timer 4
Initial State 0x00000000
TIMER 4 COUNT OBSERVATION REGISTER (TCNTO4) Register TCNTO4 Address 0x15100040 R/W R Description Timer 4 count observation register Reset Value 0x00000000
TCNTO4 Timer 4 observation register
Bit [15:0]
Description Setting count observation value for Timer 4
Initial State 0x00000000
10-19
PWM TIMER
S3C2400 RISC MICROPROCESSOR
NOTES
10-20
S3C2400 RISC MICROPROCESSOR
UART
11
OVERVIEW
UART
The S3C2400 UART (Universal Asynchronous Receiver and Transmitter) unit provides two independent asynchronous serial I/O (SIO) ports, each of which can operate in interrupt-based or DMA-based mode. In other words, UART can generate an interrupt or DMA request to transfer data between CPU and UART. It can support bit rates of up to 115.2K bps. Each UART channel contains two 16-byte FIFOs for receive and transmit. The S3C2400 UART includes programmable baud-rates, infra-red (IR) transmit/receive, one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking. Each UART contains a baud-rate generator, transmitter, receiver and control unit, as shown in Figure11-1. The baudrate generator can be clocked by PCLK. The transmitter and the receiver contain 16-byte FIFOs and data shifters. Data, which is to be transmitted, is written to FIFO and then copied to the transmit shifter. It is then shifted out by the transmit data pin (TxDn). The received data is shifted from the receive data pin (RxDn), and then copied to FIFO from the shifter.
FEATURES -- RxD0,TxD0,RxD1,TxD1 with DMA-based or interrupt-based operation -- UART Ch 0 with IrDA 1.0 & 16-byte FIFO -- UART Ch 1 with IrDA 1.0 & 16-byte FIFO -- Supports handshake transmit / receive
11-1
UART
S3C2400 RISC MICROPROCESSOR
BLOCK DIAGRAM
Peripheral BUS Transmitter Transmit Buffer Register (Transmit FIFO and Holding Register) Transmit FIFO Register(16 Byte) Transmit Holding Register (Non-FIFO mode only)
Transmit Shifter
TXDn
Control Unit
Buad-rate Generator
Clock Source
Receive Shifter
RXDn
Receive FIFO Register(16 Byte)
Receive Holding Register (Non-FIFO mode only)
Receive Buffer Register (Receive FIFO and Holding Register) Receiver
Figure 11-1. UART Block Diagram (with FIFO)
11-2
S3C2400 RISC MICROPROCESSOR
UART
UART OPERATION The following sections describe the UART operations that include data transmission, data reception, interrupt generation, baud-rate generation, loopback mode, infra-red mode, and auto flow control. Data Transmission The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register (ULCONn). The transmitter can also produce the break condition. The break condition forces the serial output to logic 0 state for one frame transmission time. This block transmits break signal after the present transmission word transmits perfectly. After the break signal transmission, it continously transmits data into the Tx FIFO (Tx holding register in the case of Non-FIFO mode). Data Reception Like the transmission, the data frame for reception is also programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits in the line control register (ULCONn). The receiver can detect overrun error, parity error, frame error and break condition, each of which can set an error flag. -- The overrun error indicates that new data has overwritten the old data before the old data has been read. -- The parity error indicates that the receiver has detected an unexpected parity condition. -- The frame error indicates that the received data does not have a valid stop bit. -- The break condition indicates that the RxDn input is held in the logic 0 state for a duration longer than one frame transmission time. Receive time-out condition occurs when it does not receive data during the 3 word time(This interval follows the setting of Word Length bit) and the Rx FIFO is not empty in the FIFO mode. Auto Flow Control(AFC) S3C2400's UART supports auto flow control with nRTS and nCTS signals, in case it would have to connect UART to UART. If users connect UART to a Modem, disable auto flow control bit in UMCONn register and control the signal of nRTS by software. In AFC, nRTS is controlled by condition of the receiver and operation of transmitter is controlled by the nCTS signal. The UART's transmitter transfers the data in FIFO only when nCTS signal active(In AFC, nCTS means that the other UART's FIFO is ready to receive data). Before the UART receives data, nRTS has to be activated when its receive FIFO has a spare more than 2-byte and has to be inactivated when its receive FIFO has a spare under 1-byte(In AFC, nRTS means that its own receive FIFO is ready to receive data).
Transmission case in UART A UART A UART B Reception case in UART A UART A UART B
TxD nCTS
RxD nRTS
RxD nRTS
TxD nCTS
Figure 11-2. UART AFC interface
11-3
UART
S3C2400 RISC MICROPROCESSOR
Non Auto-Flow control (Controlling nRTS and nCTS by S/W) Example Rx operation with FIFO 1. 2. Select receive mode (Interrupt or DMA mode) Check the value of Rx FIFO count in UFSTATn register. If the value is less than 15, users have to set the value of UMCONn[0] to '1'(activate nRTS), and if it is equal or larger than 15 users have to set the value to '0'(inactivate nRTS). Repeat item 2.
3.
Tx operation with FIFO 1. 2. Select transmit mode (Interrupt or DMA mode) Check the value of UMSTATn[0]. If the value is '1'(nCTS is activated), users write the data to Tx FIFO register.
RS-232C interface If users connect to modem interface (not equal null modem), nRTS, nCTS, nDSR, nDTR, DCD and nRI signals are need. In this case, users control these signals with general I/O ports by S/W because the AFC does not support the RS-232C interface.
11-4
S3C2400 RISC MICROPROCESSOR
UART
Interrupt/DMA Request Generation Each UART of S3C2400 has seven status(Tx/Rx/Error) signals: Overrun error, Parity error, Frame error, Break, Receive buffer data ready, Transmit buffer empty, and Transmit shifter empty, all of which are indicated by the corresponding UART status register (UTRSTATn/UERSTATn). The overrun error, parity error, frame error and break condition are referred to as the receive error status, each of which can cause the receive error status interrupt request, if the receive-error-status-interrupt-enable bit is set to one in the control register UCONn. When a receive-error-status-interrupt-request is detected, the signal causing the request can be identified by reading UERSTSTn. When the receiver transfers the data of the receive shifter to the receive FIFO and the number of received data reaches Rx FIFO Trigger Level, Rx interrupt is generated, if Receive mode in control register is selected as Interrupt request or polling mode. In the Non-FIFO mode, transfering the data of the receive shifter to the receive FIFO will cause Rx interrupt under the Interrupt request and polling mode. When the transmitter transfers data from its transmit FIFO to its transmit shifter and the number of data left in transmit FIFO reaches Tx FIFO Trigger Level, Tx interrupt is generated, if Transmit mode in control register is selected as Interrupt request or polling mode. In the Non-FIFO mode, transfering data from the transmit FIFO to the transmit shifter will cause Tx interrupt under the Interrupt request and polling mode. If the Receive mode and Transmit mode in control register are selected as the DMAn request mode then DMAn request is occurred instead of Rx or Tx interrupt in the situation mentioned above. Table 11-1. Interrupts in Connection with FIFO Type Rx interrupt FIFO Mode Each time receive data reaches the trigger level of receive FIFO, the Rx interrupt will be generated. When the number of data in FIFO does not reaches Rx FIFO trigger Level and does not receive data during 3 word time(This interval follows the setting of Word Length bit), the Rx interrupt will be generated(receive time out). Tx interrupt Each time transmit data reaches the trigger level of transmit FIFO(Tx FIFO trigger Level), the Tx interrupt will be generated. Frame error, parity error, and break signal are detected, and will generate an error interrupt. When it gets to the top of the receive FIFO without reading out data in it, the error interrupt will be generated(overrun error). Non-FIFO Mode Each time receive data becomes full, the receive holding register, generates an interrupt.
Each time transmit data become empty, the transmit holding register generates an interrupt. All errors generate an error interrupt immediately. However if another error occurs at the same time, only one interrupt is generated.
Error interrupt
11-5
UART
S3C2400 RISC MICROPROCESSOR
UART Error Status FIFO UART has the status FIFO besides the Rx FIFO register. The status FIFO indicates which data, among FIFO registers, is received with an error. The error interrupt will be issued only when the data, which has an error, is ready to read out. To clear the status FIFO, the URXHn with an error and UERSTATn must be read out. For example, It is assumed that the UART FIFO receives A, B, C, D, E characters sequentially and the frame error occurrs while receiving 'B', and the parity error occurs while receiving 'D'. Although the actual UART error occurred, the error interrupt will not be generated because the character, which was received with an error, has not been read yet. The error interrupt will occur when the character is read out. Time #0 #1 #2 #3 #4 #5 Sequence flow When no character is read out After A is read out After B is read out After C is read out After D is read out After E is read out Error interrupt - The frame error(in B) interrupt occurs - The parity error(in D) interrupt occurs - - The 'D' has to be read out The 'B' has to be read out Note
RX-FIFO break error 'E' 'D' 'C' 'B' 'A' URXHn
STATUS-FIFO parity error frame error
Error Status Generator Unit
Figure 11-3. A Case showing UART Receiving 5 Characters with 2 Errors
11-6
S3C2400 RISC MICROPROCESSOR
UART
Baud-Rate Generation Each UART's baud-rate generator provides the serial clock for transmitter and receiver. The source clock for the baud-rate generator can be selected with the S3C2400's internal system clock. The baud-rate clock is generated by dividing the source clock by 16 and a 16-bit divisor specified in the UART baud-rate divisor register (UBRDIVn). The UBRDIVn can be determined as follows: UBRDIVn = (int)(PCLK/(bps x 16) ) -1 where the divisor should be from 1 to (216-1). For example, if the baud-rate is 115200 bps and PCLK is 40 MHz, UBRDIVn is: UBRDIVn = (int)(40000000/(115200 x 16) ) -1 = (int)(21.7) -1 = 21 -1 = 20 Loop-back Mode The S3C2400 UART provides a test mode referred to as the loopback mode, to aid in isolating faults in the communication link. In this mode, the transmitted data is immediately received. This feature allows the processor to verify the internal transmit and to receive the data path of each SIO channel. This mode can be selected by setting the loopback-bit in the UART control register (UCONn).
Break Condition The break is defined as a continuous low level signal for one frame transmission time on the transmit data output.
11-7
UART
S3C2400 RISC MICROPROCESSOR
IR (Infra-Red) Mode The S3C2400 UART block supports infra-red (IR) transmission and reception, which can be selected by setting the infra-red-mode bit in the UART line control register (ULCONn). The implementation of the mode is shown in Figure 11-3. In IR transmit mode, the transmit period is pulsed at a rate of 3/16, the normal serial transmit rate (when the transmit data bit is zero); In IR receive mode, the receiver must detect the 3/16 pulsed period to recognize a zero value (refer to the frame timing diagrams shown in Figure 11-5 and 11-6 ).
TxD
0 TxD 1
UART Block
IRS 0 RxD 1 RE RxD
IrDA Tx Encoder
IrDA Rx Decoder
Figure 11-3. IrDA Function Block Diagram
11-8
S3C2400 RISC MICROPROCESSOR
UART
SIO Frame Start Bit Data Bits Stop Bit
0
1
0
1
0
0
1
1
0
1
Figure 11-4. Serial I/O Frame Timing Diagram (Normal UART)
IR Transmit Frame Start Bit Data Bits Stop Bit
0
1
0
1
0
0
1
1
0
1
Bit Time
Pulse Width = 3/16 Bit Frame
Figure 11-5. Infra-Red Transmit Mode Frame Timing Diagram
IR Receive Frame Start Bit Data Bits Stop Bit
0
1
0
1
0
0
1
1
0
1
Figure 11-6. Infra-Red Receive Mode Frame Timing Diagram
11-9
UART
S3C2400 RISC MICROPROCESSOR
UART SPECIAL REGISTERS
UART LINE CONTROL REGISTER There are two UART line control registers, ULCON0 and ULCON1, in the UART block. Register ULCON0 ULCON1 Address 0x15000000 0x15004000 R/W R/W R/W Description UART channel 0 line control register UART channel 1 line control register Reset Value 0x00 0x00
ULCONn Reserved Infra-Red Mode
Bit [7] [6]
Description
Initial State 0
The Infra-Red mode determines whether or not to use the Infra-Red mode. 0 = Normal mode operation 1 = Infra-Red Tx/Rx mode
0
Parity Mode
[5:3]
The parity mode specifies how parity generation and checking are to be performed during UART transmit and receive operation. 0xx = No parity 100 = Odd parity 101 = Even parity 110 = Parity forced/checked as 1 111 = Parity forced/checked as 0
000
Number of stop bit
[2]
The number of stop bits specifies how many stop bits are to be used to signal end-of-frame. 0 = One stop bit per frame 1 = Two stop bit per frame
0
Word length
[1:0]
The word length indicates the number of data bits to be transmitted or received per frame. 00 = 5-bits 10 = 7-bits 01 = 6-bits 11 = 8-bits
00
11-10
S3C2400 RISC MICROPROCESSOR
UART
UART CONTROL REGISTER There are two UART control registers, UCON0 and UCON1, in the UART block. Register UCON0 UCON1 Address 0x15000004 0x15004004 R/W R/W R/W Description UART channel 0 control register UART channel 1 control register Reset Value 0x00 0x00
UCONn Tx interrupt type
Bit [9]
Description Interrupt request type 0 = Pulse (Interrupt is requested as soon as Tx buffer becomes empty in Non-FIFO mode or Tx FIFO reaches Trigger Level in FIFO mode) 1 = Level (Interrupt is requested while Tx buffer is empty in NonFIFO mode or Tx FIFO has been being in Trigger Level in FIFO mode) Interrupt request type 0 = Pulse (Interrupt is requested the instant Rx buffer receives the data in Non-FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode) 1 = Level (Interrupt is requested while Rx buffer is receiving data in Non-FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode) Enable/Disable Rx time out interrupt when UART FIFO is enabled. The interrupt is a receive interrupt. 0 = Disable 1 = Enable This bit enables the UART to generate an interrupt if an exception, such as a break, frame error, parity error, or overrun error occurs during a receive operation. 0 = Do not generate receive error status interrupt 1 = Generate receive error status interrupt Setting loop-back bit to 1 causes the UART to enter the loop-back mode. This mode is provided for test purposes only. 0 = Normal operation 1 = Loop-back mode Setting this bit causes the UART to send a break during 1 frame time. This bit is auto-cleared after sending the break signal. 0 = Normal transmit 1 = Send break signal These two bits determine which function is currently able to write Tx data to the UART transmit buffer register. 00 = Disable 01 = Interrupt request or polling mode 10 = DMA0 request (Only for UART0) 11 = DMA1 request (Only for UART1) These two bits determine which function is currently able to read data from UART receive buffer register. 00 = Disable, 01 = Interrupt request or polling mode 10 = DMA0 request (Only for UART0) 11 = DMA1 request (Only for UART1)
Initial State 0
Rx interrupt type
[8]
0
Rx time out enable Rx error status interrupt enable
[7]
0
[6]
0
Loop-back Mode
[5]
0
Send Break Signal Transmit Mode
[4]
0
[3:2]
00
Receive Mode
[1:0]
00
11-11
UART
S3C2400 RISC MICROPROCESSOR
UART FIFO CONTROL REGISTER There are two UART FIFO control registers, UFCON0 and UFCON1, in the UART block. Register UFCON0 UFCON1 Address 0x15000008 0x15004008 R/W R/W R/W Description UART channel 0 FIFO control register UART channel 1 FIFO control register Reset Value 0x0 0x0
UFCONn Tx FIFO Trigger Level Rx FIFO Trigger Level Reserved Tx FIFO Reset Rx FIFO Reset FIFO Enable
Bit [7:6]
Description These two bits determine the trigger level of transmit FIFO. 00 = Empty 01 = 4-byte 10 = 8-byte 11 = 12-byte These two bits determine the trigger level of receive FIFO. 00 = 4-byte 01 = 8-byte 10 = 12-byte 11 = 16-byte
Initial State 00
[5:4]
00
[3] [2] [1] [0] This bit is auto-cleared after resetting FIFO 0 = Normal 1= Tx FIFO reset This bit is auto-cleared after resetting FIFO 0 = Normal 1= Rx FIFO reset 0 = FIFO disable 1 = FIFO mode
0 0 0 0
NOTE: When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO, the Rx interrupt will be generated (receive time out), and the users should check the FIFO status and read out the rest.
UART MODEM CONTROL REGISTER There are two UART MODEM control registers, UMCON0 and UMCON1 in the UART block. Register UMCON0 UMCON1 Address 0x1500000C 0x1500400C R/W R/W R/W Description UART channel 0 Modem control register UART channel 1 Modem control register Reset Value 0x0 0x0
UMCONn Reserved AFC (Auto Flow Control) Reserved Request to Send
Bit [7:5] [4] [3:1] [0] These bits must be 0's 0 = Disable These bits must be 0's
Description
Initial State 00
1 = Enable
0 00 0
If AFC bit is enabled, this value will be ignored. In this case the S3C2400 will control nRTS automatically. If AFC bit is disabled, nRTS must be controlled by S/W. 0 = 'H' level(Inactivate nRTS) 1 = 'L' level(Activate nRTS)
11-12
S3C2400 RISC MICROPROCESSOR
UART
UART TX/RX STATUS REGISTER There are two UART Tx/Rx status registers, UTRSTAT0 and UTRSTAT1, in the UART block. Register UTRSTAT0 UTRSTAT1 Address 0x15000010 0x15004010 R/W R R Description UART channel 0 Tx/Rx status register UART channel 1 Tx/Rx status register Reset Value 0x6 0x6
UTRSTATn Transmitter empty
Bit [2]
Description This bit is automatically set to 1 when the transmit buffer register has no valid data to transmit and the transmit shift register is empty. 0 = Not empty 1 = Transmit buffer & shifter register empty This bit is automatically set to 1 when the transmit buffer register is empty. 0 =The buffer register is not empty 1 = Empty (In Non-FIFO mode, Interrupt or DMA is requested. In FIFO mode, Interrupt or DMA is requested, when Tx FIFO Trigger Level is set to 00 (Empty)) If the UART uses the FIFO, users should check Tx FIFO Count bits and Tx FIFO Full bit in the UFSTAT register instead of this bit.
Initial State 1
Transmit buffer empty
[1]
1
Receive buffer data ready
[0]
This bit is automatically set to 1 whenever the receive buffer register contains valid data, received over the RXDn port. 0 = Empty 1 = The buffer register has a received data (In Non-FIFO mode, Interrupt or DMA is requested) If the UART uses the FIFO, users should check Rx FIFO Count bits and Rx FIFO Full bit in the UFSTAT register instead of this bit.
0
11-13
UART
S3C2400 RISC MICROPROCESSOR
UART ERROR STATUS REGISTER There are two UART Rx error status registers, UERSTAT0 and UERSTAT1, in the UART block. Register UERSTAT0 UERSTAT1 Address 0x15000014 0x15004014 R/W R R Description UART channel 0 Rx error status register UART channel 1 Rx error status register Reset Value 0x0 0x0
UERSTATn Break Detect
Bit [3]
Description This bit is automatically set to 1 to indicate that a break signal has been received. 0 = No break receive 1 = Break receive(Interrupt is requested) This bit is automatically set to 1 whenever a frame error occurs during receive operation. 0 = No frame error during receive 1 = Frame error(Interrupt is requested) This bit is automatically set to 1 whenever a parity error occurs during receive operation. 0 = No parity error during receive 1 = Parity error(Interrupt is requested) This bit is automatically set to 1 whenever an overrun error occurs during receive operation. 0 = No overrun error during receive 1 = Overrun error(Interrupt is requested)
Initial State 0
Frame Error
[2]
0
Parity Error
[1]
0
Overrun Error
[0]
0
NOTE:
These bits (UERSATn[3:0]) are automatically cleared to 0 when the UART error status register is read.
11-14
S3C2400 RISC MICROPROCESSOR
UART
UART FIFO STATUS REGISTER There are two UART FIFO status registers, UFSTAT0 and UFSTAT1, in the UART block. Register UFSTAT0 UFSTAT1 Address 0x15000018 0x15004018 R/W R R Description UART channel 0 FIFO status register UART channel 1 FIFO status register Reset Value 0x00 0x00
UFSTATn Reserved Tx FIFO Full
Bit [15:10] [9]
Description
Initial State 0
This bit is automatically set to 1 whenever transmit FIFO is full during transmit operation 0 = 0-byte Tx FIFO data 15-byte 1 = Full This bit is automatically set to 1 whenever receive FIFO is full during receive operation 0 = 0-byte Rx FIFO data 15-byte 1 = Full Number of data in Tx FIFO Number of data in Rx FIFO
0
Rx FIFO Full
[8]
0
Tx FIFO Count Rx FIFO Count
[7:4] [3:0]
0 0
11-15
UART
S3C2400 RISC MICROPROCESSOR
UART MODEM STATUS REGISTER There are two UART modem status registers, UMSTAT0 and UMSTAT1, in the UART block. Register UMSTAT0 UMSTAT1 Address 0x1500001C 0x1500401C R/W R R Description UART channel 0 Modem status register UART channel 1 Modem status register Reset Value 0x0 0x0
UMSTAT0 Reserved Delta CTS
Bit [3] [2]
Description
Initial State 0
This bit indicates that the nCTS input to S3C2400 has changed state since the last time it was read by CPU. (Refer to Figure 11-7) 0 = Has not changed 1 = Has changed
0
Reserved Clear to Send
[1] [0] 0 = CTS signal is not activated(nCTS pin is high) 1 = CTS signal is activated(nCTS pin is low)
0 0
nCTS
Delta CTS
Read_UMSTAT
Figure 11-7. nCTS and Delta CTS Timing Diagram
11-16
S3C2400 RISC MICROPROCESSOR
UART
UART TRANSMIT BUFFER REGISTER(HOLDING REGISTER & FIFO REGISTER) UTXHn has an 8-bit data for transmission data Register UTXH0 UTXH1 Address 0x15000020(L) 0x15000023(B) 0x15004020(L) 0x15004023(B) R/W Description Reset Value - -
W UART channel 0 transmit buffer register (by byte) W UART channel 1 transmit buffer register (by byte)
UTXHn TXDATAn
NOTE:
Bit [7:0] Transmit data for UARTn
Description
Initial State -
(L): When the endian mode is Little endian. (B): When the endian mode is Big endian.
UART RECEIVE BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) URXHn has an 8-bit data for received data Register URXH0 URXH1 Address 0x15000024(L) 0x15000027(B) 0x15004024(L) 0x15004027(B) R/W Description Reset Value - -
R UART channel 0 receive buffer register (by byte) R UART channel 1 receive buffer register (by byte)
URXHn RXDATAn
NOTE:
Bit [7:0] Receive data for UARTn
Description
Initial State -
When an overrun error occurs, the URXHn must be read. If not, the next received data will also make an overrun error, even though the overrun bit of USTATn had been cleared.
11-17
UART
S3C2400 RISC MICROPROCESSOR
UART BAUD RATE DIVISION REGISTER The value stored in the baud rate divisor register, UBRDIV, is used to determine the serial Tx/Rx clock rate (baud rate) as follows: UBRDIVn = (int)(PCLK / (bps x 16) ) -1
where the divisor should be from 1 to (216-1). For example, if the baud-rate is 115200 bps and PCLK is 40 MHz , UBRDIVn is: UBRDIVn = (int)(40000000 / (115200 x 16) ) -1 = (int)(21.7) -1 = 21 -1 = 20
Register UBRDIV0 UBRDIV1
Address 0x15000028 0x15004028
R/W R/W R/W
Description Baud rate divisior register 0 Baud rate divisior register 1
Reset Value - -
UBRDIV n UBRDIV
Bit [15:0] Baud rate division value UBRDIVn > 0
Description
Initial State -
11-18
S3C2400X RISC MICROPROCESSOR
USB HOST
12
OVERVIEW
* * * *
USB HOST CONTROLLER
S3C2400 supports 2 port USB host interface as follows; Open HCI Rev 1.0 compatible. USB Rev1.1 compatible 2 down stream ports. Support for both LowSpeed and HighSpeed USB devices
OHCI ROOT HUB REGS APP_SADR(8) APP_SDATA(32) HCI_DATA(32) CONTROL OHCI REGS CONTROL 1 PORT S/M TxEnl ROOT HUB & HOST SIE TxDpls TxDmns PORT S/M X USB V R 2 X USB V R
HCI SLAVE BLOCK
RCF0_RegData(32) CONTROL USB STATE CONTROL Cntl CONTROL
APP_MDATA(32) HCI BUS
HCM_ADR/ DATA(32)
CONTROL
HCI MASTER BLOCK
LIST ED/TD_DATA(32) PROCESSOR BLOCK ED/TD STATUS(32) ED&TD REGS
CTRL CTRL
RcvData HSIE S/M RH_DATA(8) DF_DATA(8) DPLL RcvDpls RcvDmns
ROOT HUB & HOST SIE
STATUS HC_DATA(8) DF_DATA(8) HCF_DATA(8) 64x8 FIFO Cntl Addr(6) FIFO_DATA(8)
PORT S/M
EXT.FIFO STATUS
64x8 FIFO
Figure 12-1. USB Host Controller Block Diagram
12-1
USB HOST
S3C2400 RISC MICROPROCESSOR
USB HOST CONTROLLER SPECIAL REGISTERS
The S3C2400 USB Host controller complies with OPEN HCI Rev 1.0. Please refer to Open Host Controller Interface Rev 1.0 specification for detail information.
OHCI REGISTERS FOR USB HOST CONTROLLER Register HcRevision HcControl HcCommonStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCuttentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcRmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2 Base Address 0x14200000 0x14200004 0x14200008 0x1420000c 0x14200010 0x14200014 0x14200018 0x1420001c 0x14200020 0x14200024 0x14200028 0x1420002c 0x14200030 0x14200034 0x14200038 0x1420003c 0x14200040 0x14200044 0x14200048 0x1420004c 0x14200050 0x14200054 0x14200058 R/W - - - - - - - - - - - - - - - - - - - - - - - Root hub group Frame counter group Memory pointer group Description Control and status group Reset Value - - - - - - - - - - - - - - - - - - - - - - -
12-2
S3C2400 RISC MICROPROCESSOR
USB DEVICE
13
OVERVIEW
USB DEVICE
USB function controller is designed to provide a high performance full speed function controller solution with DMA I/F.USB function controller allows bulk transfer with DMA, interrupt transfer and control transfer. The integrated on-chip functions are as follows: -- Full Speed USB Function Controller compatible with the USB Specification Version 1.1 -- DMA Interface for Bulk Transfer -- 5 Endpoint with FIFO EP0: 16byte (dual port asynchronous ram) EP1: 64byte IN FIFO (single port asynchronous ram): interrupt and DMA EP2: 64byte IN FIFO (single port asynchronous ram): interrupt EP3: 64byte OUT FIFO (single port asynchronous ram): interrupt and DMA EP4: 64byte OUT FIFO (single port asynchronous ram): interrupt -- Integrated USB Transceiver (ASIC USB Pad) FEATURES -- Fully compliant to USB Specification Version 1.1 -- Full Speed (12Mbps) Device -- Integrated USB Transceiver (ASIC USB Pad) -- Supports Control, Interrupt and Bulk transfer -- 5 Endpoint with FIFO: One Bi-directional Control Endpoint with 16 byte FIFO (EP0) Two Receive Bulk Endpoint with 64 byte FIFO (EP1, EP2) Two Transmit Bulk Endpoint with 64 byte FIFO (EP3, EP4) -- Supports DMA interface for receive and transmit bulk endpoints. (EP1, EP2, EP3, EP4) -- Independent 64byte receive and transmit FIFO to maximize throughput -- Support suspend and remote wake-up function -- Operating Frequency: 48MHz -- Not support ISO transfer
13-1
USB DEVICE
S3C2400 RISC MICROPROCESSOR
MC_ADDR[13:0] RT_VM_IN MC_DATA_IN[31:0]
SIU
RT_VP_IN RXD SYS_CLK RT_VP_OUT RT_VM_OUT RT_UX_OEN MC_CSN RT_UXSUSPEND MC_DATA_OUT[31:0] USB_CLK
SIE
MCU & DMA I/F
SYS_RESETN MC_WR WR_RDN
GFI
MC_INTR DREQN DACKN
Vin
FIFOs
Power Detect
Vout
Figure 13-1. USB Device Block Diagram
13-2
S3C2400X01 RISC MICROPROCESSOR
USB DEVICE
USB DEVICE SPECIAL REGISTERS
This section describes the detail functionality about register set USB Device. All Special Function Register is Word Access. Reserved bit is zero. All Register must be set after Host Reset Signaling. FUNCTION ADDRES REGISTER (FUNC_ADDR_REG) This register maintains the USB Device Address assigned by the host. The S3C2400 writes the value received through a SET_ADDRESS descriptor to this register. This address is used for the next token.
Register FUNC_ADDR_REG
Address 0x15200140
R/W R/W
Description Function address register
Reset Value 0x00000000
FUNC_ADDR_REG Reserved ADDR_UPDATE
Bit [31:8] [7]
MCU R SET
USB
Description
Initial State 0
R /CLEAR
The MCU sets this bit whenever it updates the FUNCTION_ADDR field in this register. This bit will be cleared by USB when DATA_END bit in EP0_CSR register.
0
FUNCTION_ADDR
[6:0]
R/W
R
The MCU write the unique address, assigned by host, to this field.
0000000
13-3
USB DEVICE
S3C2400 RISC MICROPROCESSOR
POWER MANAGEMENT REGISTER (PWR_REG) This register is power control register in USB block. Register PWR_REG FUNC_ADDR Reserved CLK_MASK Address 0x15200144 Bit [31:9] [8] R/W R The MCU sets this bit to mask USB clock: 0 = Normal operation, 1 = USB clock mask Clear Method : The MCU writes `high' on the MCU_RESET(bit [7]). MCU_RESET [7] W R The MCU sets this bit to reset USB: 0 = Normal operation, 1 = S/W Reset Clear Method: The MCU write 'low' on this bit. EP0_FLUSH VBUS_STATUS Reserved USB_RESET [6] [5] [4] [3] R/W R - R R W - SET The USB sets this bit if reset signaling is received from the host. This bit remains set as long as reset signaling persists on the bus The MCU sets this bit for MCU resume. The USB generates the resume signaling depending RESUME CON Register, while this bit is set in suspend mode. This bit can be set by USB, automatically when the device enter into suspend mode. It can be cleared under the MCU or USB resume conditions. SUSPEND_EN [0] R/W R Suspend mode enable control bit: 0 = Disable (default) 1 = Enable Disables masked suspend mode 0 0 The MCU sets this bit to flush EP0 FIFO VBUS monitoring bit 0 0 0 0 0 MCU R/W R/W USB Description Power management register Description Reset Value 0x00000000 Initial State 0
MCU_RESUME
[2]
W
R /CLEAR
SUSPEND_MODE
[1]
R
SET /CLEAR
13-4
S3C2400X01 RISC MICROPROCESSOR
USB DEVICE
INTERRUPT REGISTER (INT_REG) These registers act as status registers for the MCU when there is an interrupt event. The bits in these registers are cleared by the MCU by writing a 1(Not "0") to each bit. Once the MCU is interrupted, MCU should read the contents of interrupt-related registers and write back to clear the contents if it is necessary. Register INT_REG Address 0x15200148 R/W R Description Interrupt pending/clear register Reset Value 0x00000000
INT_REG ERROR Interrupt RESET Interrupt RESUME Interrupt
Bit [8]
MCU R /CLEAR R /CLEAR R /CLEAR
USB SET
Description Error monitoring interrupt source. It can be set under the following conditions: 1. crc error 2. bit stuff error Reset interrupt It can be set under the following conditions: 1. USB Reset 2. MCU Reset The USB sets this bit, when it receives the Resume signaling (Resume Command in USB bus), while in Suspend mode. If the Resume is due to a USB reset, then the MCU is first interrupted into a RESUME interrupt. The USB sets this bit when it receives the Suspend signaling. This bit is set whenever there is no activity during 3ms on the USB bus. Thus, if the MCU does not stop the clock after the first Suspend interrupt, that it will be continually to be interrupted every 3ms as long as there is no activity on the USB bus. By default, this interrupt is masked.
Initial State 0
[7]
SET
0
[6]
SET
0
SUSPEND Interrupt
[5]
R /CLEAR
SET
0
EP4 Interrupt EP3 Interrupt EP2 Interrupt EP1 Interrupt EP0 Interrupt
[4]
R /CLEAR R /CLEAR R /CLEAR R /CLEAR R /CLEAR
SET
Endpoint4 interrupt: 1. Sets OUT_PKT_RDY bit.(EP4_OUT_CSR1[0]) 2. Sets SENT_STALL bit.(EP4_OUT_CSR1[6]) Endpoint3 interrupt: 1. Sets OUT_PKT_RDY bit.(EP3_OUT_CSR1[0]) 2. Sets SENT_STALL bit.(EP3_OUT_CSR1[6]) Endpoint2 interrupt: 1. IN_PKT_RDY is cleared.(EP2_IN_CSR1[0]) 2. FIFO is flushed.(EP2_IN_CSR[2]) Endpoint1 interrupt: 1. IN_PKT_RDY is cleared.(EP1_IN_CSR1[0]) 2. FIFO is flushed.(EP1_IN_CSR[2]) Endpoint0 interrupt: 1. OUT_PKT_RDY bit (D0) is set.(EP0_CSR[0]) 2. IN_PKT_RDY bit (D1) is cleared.(EP0_CSR[1]) 3. SENT_STALL bit (D2) is set.(EP0_CSR[2]) 4. SETUP_END bit (D4) is set.(EP0_CSR[4]) 5. DATA_END bit is cleared.(EP0_CSR[3]) (Indicates End of control transfer)
0
[3]
SET
0
[2]
SET
0
[1]
SET
0
[0]
SET
0
13-5
USB DEVICE
S3C2400 RISC MICROPROCESSOR
INTERRUPT MASK REGISTER (INT_MASK_REG) This register can mask interrupt(except RESUME Interrupt). Register INT_MASK_REG Address 0x1520014C R/W R/W Description Determines which interrupt is masked. The masked interrupt will not be serviced. 0 = Interrupt is available 1 = Interrupt is masked Reset Value 0x033F
INT_MASK_REG Reserved CRC_MASK
Bit [31:10] [9]
MCU
USB
Description
Initial State 0
R/W
R
CRC Error Interrupt Mask bit: 0 = Interrupt enable 1 = Masked BIT_STUFF Error interrupt Mask bit: 0 = Interrupt enable 1 = Masked RESET Interrupt Mask bit: 0 = Interrupt enable 1 = Masked
1
BIT_STUFF_MASK
[8]
R/W
R
1
RESET_MASK
[7]
R/W
R
0
Reserved SUSPEND_MASK
[6] [5] R/W R SUSPEND Interrupt Mask bit: 0 = Interrupt enable 1 = Masked EP4 Interrupt Mask bit: 0 = Interrupt enable 1 = Masked EP3 Interrupt Mask bit: 0 = Interrupt enable 1 = Masked EP2 Interrupt Mask bit: 0 = Interrupt enable 1 = Masked EP1 Interrupt Mask bit: 0 = Interrupt enable 1 = Masked EP0 Interrupt Mask bit: 0 = Interrupt enable 1 = Masked
0 1
EP4_MASK
[4]
R/W
R
1
EP3_MASK
[3]
R/W
R
1
EP2_MASK
[2]
R/W
R
1
EP1_MASK
[1]
R/W
R
1
EP0_MASK
[0]
R/W
R
1
13-6
S3C2400X01 RISC MICROPROCESSOR
USB DEVICE
FRAME NUMBER REGISTER (FPAME_NUM_REG) When host transfer USB packet, there is frame number in SOF(Start Of Frame). The USB catch this frame number and load it into this register, automatically. Register FRAME_NUM_REG Address 0x15200150 R/W R Description Frame number register Reset Value 0x00000000
FRAME_NUM_REG Reserved FRAME_NUM
Bit [31:11] [10:0]
MCU
USB
Description
Initial State 0
R
W
Frame number value
00000000000
RESUME SIGNAL CONTROL REGISTER (RESUME_CON_REG) This register can control resume signal length. 5-bit down counts. Register RESUME_CON_REG Address 0x15200154 R/W R/W Description Resume signal control register Reset Value 0x000A
RESUME_CON_REG Reserved RESUME_CON
Bit [31:5] [4:0]
MCU
USB
Description
Initial State 0
R/W
R
The value of these 5-bits means the length of resume signal. The unit is mili-second. 00000 = Can not be used 00001 = 1 ms 00010 = 2 ms 00011 = 3 ms 00100 = 4 ms 00101 = 5 ms 00110 = 6 ms 00111 = 7 ms 01000 = 8 ms 01001 = 9 ms 01010 = 10 ms 01011 = 11 ms 01100 = 12 ms 01101 = 13 ms 01110 = 14 ms 01111 = 15 ms 10000 = 16 ms 10001 = 17 ms 10010 = 18 ms 10011 = 19 ms 10100 = 20 ms 10101 = 21 ms 10110 = 22 ms 10111 = 23 ms 11000 = 24 ms 11001 = 25 ms 11010 = 26 ms 11011 = 27 ms 11100 = 28 ms 11101 = 29 ms 11110 = 30 ms 11111 = 31 ms
01010
13-7
USB DEVICE
S3C2400 RISC MICROPROCESSOR
END POINT0 CONTROL STATUS REGISTER (EP0_CSR) Register EP0_CSR Address 0x15200160 R/W R/W Description Clock generator control Register Reset Value 0x00000000
EP0_CSR Reserved SERVICED_SETUP _END SERVICED_OUT_P KT_RDY SEND_STALL
Bit [31:8] [7] [6] [5]
MCU W W R/W
USB CLEAR CLEAR CLEAR
Description The MCU should write a "1" to this bit to clear SETUP_END The MCU should write a "1" to this bit to clear OUT_PKT_RDY The MCU should writes a "1" to this bit at the same time it clears OUT_PKT_RDY, if it decodes an invalid token. 0 = Finish the STALL condition 1 = The USB issues a STALL and shake to the current control transfer. The USB sets this bit when a control transfer ends before DATA_END is set. When the USB sets this bit, an interrupt is generated to the MCU. When such a condition occurs, the USB flushes the FIFO and invalidates MCU access to the FIFO. The MCU sets this bit below conditions: 1. After loading the last packet of data into the FIFO, at the same time IN_PKT_RDY is set. 2. While it clears OUT_PKT_RDY after unloading the last packet of data. 3. For a zero length data phase. The USB sets this bit if a control transaction is stopped due to a protocol violation. An interrupt is generated when this bit is set. The MCU should write "0" to clear this bit. The MCU sets this bit after writing a packet of data into EP0 FIFO. The USB clears this bit once the packet has been successfully sent to the host. An interrupt is generated when the USB clears this bit, so as the MCU to load the next packet. For a zero length data phase, the MCU sets DATA_END at the same time. The USB sets this bit once a valid token is written to the FIFO. An interrupt is generated when the USB sets this bit. The MCU clears this bit by writing a "1" to the SERVICED_OUT_PKT_RDY bit.
Initial State 0 0 0 0
SETUP_END
[4]
R
SET
0
DATA_END
[3]
SET
CLEAR
0
SENT_STALL
[2]
CLEAR
SET
0
IN_PKT_RDY
[1]
SET
CLEAR
0
OUT_PKT_RDY
[0]
R
SET
0
13-8
S3C2400X01 RISC MICROPROCESSOR
USB DEVICE
END POINT0 MAX PACKET REGISTER (EP0_MAXP) Register EP0_MAXP Address 0x15200164 R/W R/W Description End Point0 MAX packet register Reset Value 0x00000001
EP0_MAXP Reserved EP0_MAXP
Bit [31:2] [1:0]
MCU
USB
Description
Initial State 0
R/W
R
00: MAXP = 0 01: MAXP = 8 10: MAXP = 16
01
END POINT0 OUT WRITE COUNT REGISTER (EP0_OUT_CNT) This register has the number of bytes consist of one packet. Initially, OUT Write Count Register should keep the number of bytes consisting one packet and MCU should fetches number of bytes as many bytes as this register value indicates. Register EP0_OUT_CNT Address 0x15200168 R/W R/W Description End Point0 out write count register Reset Value 0x00000000
EP0_OUT_CNT Reserved OUT_CNT
Bit [31:5] [4:0]
MCU
USB
Description
Initial State 0
R/W
R
EP0 out write count value
00000
END POINT0 FIFO READ/WRITE REGISTER (EP0_FIFO) End Point0 is for input or output to host. To access EP0 FIFO, the MCU should access FIFO through EP0_FIFO register. Lower 8-bit is valid. Register EP0_FIFO Address 0x1520016C R/W R/W Description End Point0 FIFO read/write register Reset Value 0x000000xx
EP0_FIFO Reserved FIFO_DATA
Bit [31:8] [7:0]
MCU
USB
Description
Initial State 0
R/W
R/W
EP0 FIFO data values
0Xxx
13-9
USB DEVICE
S3C2400 RISC MICROPROCESSOR
END POINT IN CONTROL STATUS REGISTER Register EP1_IN_CSR EP2_IN_CSR Address 0x15200180 0x15200190 R/W R/W R/W Description END POINT1 in control status register END POINT2 in control status register Reset Value 0x00000000 0x00000000
EPn_IN_CSR Reserved AUTO_SET
Bit [31:8] [7]
MCU
USB
Description
Initial State 0
R/W
R
In case of single packet mode, if the packet size is same as FIFO size, IN_PKT_RDY bit can be set automatically (AUTO_SET=1) when MCU write a packet data into FIFO. This is a special feature in case that the single packet size is same as FIFO size. If it's not this case, MCU should set IN_PKT_RDY as explained in EPn_IN_CSR register. This bit determines whether the interrupt should be issued, or not, when the EP1 IN_PKT_RDY condition happens. This is only useful for DMA mode. 0 = Interrupt enable, 1 = Interrupt Masking This bit can be used in Set-up procedure. 0 = There are alternation of DATA0 and DATA1. 1 = The data toggle bit is cleared and PID in packet will maintain DATA0. The USB sets this bit when an IN token issues a STALL handshake, after the MCU sets SEND_STALL bit to start STALL handshaking. When the USB issues a STALL handshake, IN_PKT_RDY is cleared.
0
DMA_IPR_IN_MASK
[6]
R/W
R
0
CLR_DATA_TOGGLE
[5]
R/W
R/ CLEAR
0
SENT_STALL
[4]
R/ CLEAR
SET
0
SEND_STALL
[3]
W/R
R
0 = The MCU clears this bit to finish the STALL condition. 1 = The MCU issues a STALL and shake to the USB.
0
13-10
S3C2400 RISC MICROPROCESSOR
USB DEVICE
EPn_IN_CSR FIFO_FLUSH
Bit [2]
MCU W/ CLEAR
USB CLEAR
Description The MCU sets this bit if it intends to flush the packet in Input-related FIFO. This bit is cleared by the USB when the FIFO is flushed. The MCU is interrupted when this happens. If a token is in process, the USB waits until the transmission is complete before FIFO flushing. If two packets are loaded into the FIFO, only first packet (The packet is intended to be sent to the host) is flushed, and the corresponding IN_PKT_RDY bit is cleared
Initial State 0
Reserved IN_PKT_RDY
[1] [0] SET/ R CLEAR The MCU sets this bit after writing a packet data into the FIFO. The USB clears this bit once the packet has been successfully sent to the host. An interrupt is generated when the USB clears this bit so as the MCU to load the next packet. While this bit is set by MCU after writing a packet data into the FIFO, the MCU will not be able to write a new packet data to the FIFO without clearing by USB. If the SEND_STALL bit is set by the MCU, this bit also cannot be set.
0 0
13-11
USB DEVICE
S3C2400 RISC MICROPROCESSOR
END POINT IN MAX PACKET REGISTER Register EP1_IN_MAXP EP2_IN_MAXP Address 0x15200184 0x15200194 R/W R/W R/W Description End Point1 in MAX packet register End Point2 in MAX packet register Reset Value 0x00000001 0x00000001
EPn_IN_MAXP Reserved IN_MAXP
Bit [31:4] [3:0]
MCU
USB
Description
Initial State 0
R/W
R
0000 : MAXP = 0 0001 : MAXP = 8 0010 : MAXP = 16 0011 : MAXP = 24 0100 : MAXP = 32 0101 : MAXP = 40 0110 : MAXP = 48 0111 : MAXP = 56 1000 : MAXP = 64
0001
END POINT IN FIFO WRITE REGISTER End Point1 or End Point2 is for output to host. To access EP1 FIFO or EP2 FIFO, the MCU should access FIFO through EP1_FIFO register or EP2_FIFO register. Lower 8-bit is valid. Register EP1_FIFO EP2_FIFO Address 0x15200188 0x15200198 R/W W W Description End Point1 FIFO write register End Point2 FIFO write register Reset Value 0x000000xx 0x000000xx
EPn_FIFO Reserved IN_FIFO_DATA
Bit [31:8] [7:0]
MCU
USB
Description
Initial State 0
W
R
IN FIFO data value
0Xxx
13-12
S3C2400X01 RISC MICROPROCESSOR
USB DEVICE
END POINT OUT CONTROL STATUS REGISTER Register EP3_OUT_CSR EP4_OUT_CSR Address 0x152001A0 0x152001B0 R/W R/W R/W Description End Point3 out control status register End Point4 out control status register Reset Value 0x00000000 0x00000000
EPn_OUT_CSR Reserved AUTO_CLR
Bit [31:8] [7]
MCU R/W
USB R
Description If MCU set, whenever the MCU reads data from the OUT FIFO, OUT_PKT_RDY will automatically be cleared by the logic, without any intervention from MCU. This bit determines whether the interrupt should be issued, or not, when the EP3 OUT_PKT_RDY condition happens. This is only useful for DMA mode 0 = Interrupt Enable 1 = Interrupt Masking When the MCU writes a 1 to this bit, the data toggle sequence bit is reset to DATA0. The USB sets this bit when an OUT token is ended with a STALL handshake. The USB issues a stall handshake to the host if it sends more than MAXP data for the OUT TOKEN. 0 = The MCU clears this bit to end the STALL condition handshake, IN PKT RDY is cleared. 1 = The MCU issues a STALL handshake to the USB. The MCU clears this bit to end the STALL condition handshake, IN PKT RDY is cleared. The MCU write a 1 to flush the FIFO. This bit can be set only when OUT_PKT_RDY (D0) is set. The packet due to be unloaded by the MCU will be flushed. The USB sets this bit after it has loaded a packet of data into the FIFO. Once the MCU reads the packet from FIFO, this bit should be cleared by MCU. (Write a "0")
Initial State 0 0
DMA_OPR_INT _MASK
[6]
R/W
R
0
CLR_DATA _TOGGLE SENT_STALL
[5]
R/W
CLEAR
0
[4]
CLEAR /R
SET
0
SEND_STALL
[3]
R/W
R
0
FIFO_FLUSH
[2]
R/W
CLEAR
0
Reserved OUT_PKT_RDY
[1] [0] R/ CLEAR SET
0 0
13-13
USB DEVICE
S3C2400 RISC MICROPROCESSOR
END POINT OUT MAX PACKET REGISTER Register EP3_OUT_MAXP EP4_OUT_MAXP Address 0x152001A4 0x152001B4 R/W R/W R/W Description End Point3 out MAX packet register End Point4 out MAX packet register Reset Value 0x00000001 0x00000001
EPn_IN_MAXP Reserved OUT_MAXP
Bit [31:4] [3:0]
MCU
USB
Description
Initial State 0
R/W
R
0000 : MAXP = 0 0001 : MAXP = 8 0010 : MAXP = 16 0011 : MAXP = 24 0100 : MAXP = 32 0101 : MAXP = 40 0110 : MAXP = 48 0111 : MAXP = 56 1000 : MAXP = 64
0001
END POINT OUT WRITE COUNT REGISTER This register has the number of bytes consist of one packet. Initially, OUT Write Count Register should keep the number of bytes consisting one packet and MCU should fetches number of bytes as many bytes as this register value indicates. Register EP3_OUT_CNT EP4_OUT_CNT Address 0x152001A8 0x152001B8 R/W R R Description End Point3 out write count register End Point4 out write count register Reset Value 0x00000000 0x00000000
EPn_OUT_CNT Reserved OUT_CNT
Bit [31:7] [6:0]
MCU
USB
Description
Initial State 0
R
W
Out write count value
0000000
13-14
S3C2400X01 RISC MICROPROCESSOR
USB DEVICE
END POINT FIFO READ REGISTER End Point3 or End Point4 is for output to MCU. To access EP3 FIFO or EP4 FIFO, the MCU should access FIFO through EP3_FIFO Register or EP4_FIFO Register. Lower 8-bit is valid. Register EP3_FIFO EP4_FIFO Address 0x152001AC 0x152001BC R/W R R Description End Point3 FIFO read register End Point4 FIFO read register Reset Value 0x000000xx 0x000000xx
EPn_FIFO Reserved OUT_FIFO_DATA
Bit [31:8] [7:0]
MCU
USB
Description
Initial State 0
R
W
Out FIFO data value
0Xxx
DMA INTERFACE CONTROL REGISTER (DMA_CON) Register DMA_CON Address 0x152001C0 R/W R/W Description DMA interface control register Reset Value 0x00000000
CLKCON Reserved IN_RUN_OB STATE DEMAND_MODE
Bit [31:8] [7] [6:4] [3]
MCU
USB
Description
Initial State 0
R R R/W
W W R
In DMA Run Observation DMA State Monitoring Demand Mode Enable 0 = Disable 1 = Enable
0 0 0
OUT_DMA_RUN
[2]
R/W
CLEAR
This bit is used to start DMA operation for End Point3 0 = Stop 1 = Run This bit is used to start DMA operation for End Point1 0 = Stop 1 = Run This bit is used to set DMA mode 0 = Interrupt Mode 1 = DMA Mode for Bulk Endpoint
0
IN_DMA_RUN
[1]
R/W
CLEAR
0
DMA_MODE_EN
[0]
R/W
R
0
13-15
USB DEVICE
S3C2400 RISC MICROPROCESSOR
DMA UNIT COUNTER REGISTER (DMA_UNIT) 8-bit counter to setting DMA transfer unit. Register DMA_UNIT Address 0x152001C4 R/W R/W Description DMA transfer unit counter base register Reset Value 0x00000000
DMA_UNIT UNIT_CNT
Bit [7:0]
MCU R/W
USB R
Description DMA transfer unit counter value
Initial State 0x00
DMA FIFO COUNTER REGISTER (DMA_FIFO) This register has byte size in FIFO to be transferred by DMA. In case of EP3 as soon as OUT_STR_DMA_RUN enable, the value in OUT FIFI Write Count Register1 will be loaded in this register automatically. In case of EP1, the MCU should set proper value by S/W. Register DMA_FIFO Address 0x152001C8 R/W R/W Description DMA transfer FIFO counter base register Reset Value 0x00000000
DMA_FIFO Reserved FIFO_CNT
Bit [31:8] [7:0]
MCU
USB
Description
Initial State 0
R/W
R
DMA transfer FIFO counter value
0x00
DMA TX COUNTER REGISTER (DMA_TX) This register (24-bit) should have total number of bytes to be transferred using DMA. Register DMA_TX Address 0x152001CC R/W R/W Description DMA total transfer counter base register Reset Value 0x00000000
DMA_TX Reserved TX_CNT
Bit [31:24] [23:0]
MCU
USB
Description
Initial State 0
R/W
R
DMA total transfer count value
0x000000
13-16
S3C2400X01 RISC MICROPROCESSOR
USB DEVICE
TEST MODE CONTROL REGISTER (TEST_MODE) Don't write this register in normal operation. Register TEST_MODE Address 0x152001F4 R/W W Description Test mode control register Reset Value 0x00000000
TEST_MODE Reserved EP1234_MEM _TEST
Bit [31:2] [1]
MCU
USB
Description
Initial State 0
W
R
The MCU sets this bit to test EP1, EP2, EP3, and EP4 FIFO memory. This is set, and then the MCU can access EP1, EP2, EP3, and EP4 FIFO memory directly. 0 = Test disable (Normal operation mode) 1 = Test enable The MCU sets this bit to test EP0 FIFO memory. This is set, and then the MCU can access EP0 FIFO memory directly. 0 = Test disable (Normal operation mode) 1 = Test enable
0
EP0_MEM_TEST
[0]
W
R
0
IN PACKET NUMBER CONTROL REGISTER (IN_CON_REG) This register can control number of in packet terms of SOF(Start Of Frame) Register IN_CON_REG Address 0x152001F8 R/W W Description In packet number control register Reset Value 0x00FF
IN_CON_REG Reserved IN_CON_MASK
Bit [31:8] [7]
MCU
USB
Description
Initial State 0
W
R
IN CON function masking 0 = Enable 1 = Masked (Normal operation mode) This data is number of in packet terms of SOF. If this data were 3, USB Device responses NAK to 4th in packet.
1
IN_CON
[6:0]
W
R
1111111
13-17
USB DEVICE
S3C2400 RISC MICROPROCESSOR
NOTES
13-18
S3C2400 RISC MICROPROCESSOR
INTERRUPT CONTROLLER
14
OVERVIEW
INTERRUPT CONTROLLER
The interrupt controller in S3C2400 receives the request from 32interrupt sources. These interrupt sources are provided by internal peripheral such as the DMA controller, UART and IIC, etc. In these interrupt sources, the UART0 and UART1 error interrupts are 'OR'ed to the interrupt controller. The role of the interrupt controller is to ask for the FIQ or IRQ interrupt requests to the ARM920T core after the arbitration process when there are multiple interrupt requests from internal peripherals and external interrupt request pins. The arbitration process is performed by the hardware priority logic and the result is written to the interrupt pending register and users notice that register to know which interrupt has been requested.
SRCPND
MASK Priority MODE
INTPND IRQ
FIQ
Figure 14-1. Interrupt Process Diagram
14-1
INTERRUPT CONTROLLER
S3C2400 RISC MICROPROCESSOR
INTERRUPT CONTROLLER OPERATION F-bit and I-bit of PSR (program status register) If the F-bit of PSR (program status register in ARM920T CPU) is set to 1, the CPU does not accept the FIQ (fast interrupt request) from the interrupt controller. If I-bit of PSR (program status register in ARM920T CPU) is set to 1, the CPU does not accept the IRQ (interrupt request) from the interrupt controller. So, to enable the interrupt reception, the F-bit or I-bit of PSR has to be cleared to 0 and also the corresponding bit of INTMSK has to be set to 0. Interrupt Mode ARM920T has 2 types of interrupt mode, FIQ or IRQ. All the interrupt sources determine the mode of interrupt to be used at interrupt request. Interrupt Pending Register S3C2400X01 has two interrupt pending resisters. The one is source pending register(SRCPND), the other is interrupt pending register(INTPND). These pending registers indicate whether or not an interrupt request is pending. When the interrupt sources request interrupt service the corresponding bits of SRCPND register are set to 1, at the same time the only one bit of INTPND register is set to 1 automatically after arbitration process. If interrupts are masked, the corresponding bits of SRCPND register are set to 1, but the bit of INTPND register is not changed. When a pending bit of INTPND register is set, the interrupt service routine starts whenever the I-flag or F-flag is cleared to 0. The SRCPND and INTPND registers can be read and written, so the service routine must clear the pending condition by writing a 1 to the corresponding bit in SRCPND register first and then clear the pending condition in INTPND registers same method. Interrupt Mask Register Indicates that an interrupt has been disabled if the corresponding mask bit is 1. If an interrupt mask bit of INTMSK is 0, the interrupt will be serviced normally. If the corresponding mask bit is 1 and the interrupt is generated, the source pending bit will be set.
14-2
S3C2400 RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTERRUPT SOURCES Interrupt controller supports 32 interrupt sources as shown in below table. Two UART error interrupt requests are Ored to provide a single interrupt source to the interrupt controller. Sources INT_ADC INT_RTC INT_UTXD1 INT_UTXD0 INT_IIC INT_USBH INT_USBD INT_URXD1 INT_URXD0 INT_SPI INT_MMC INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 Reserved INT_UERR0/1 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 Descriptions ADC EOC interrupt RTC alarm interrupt UART1 transmit interrupt UART0 transmit interrupt IIC interrupt USB Host interrupt USB Device interrupt UART1 receive interrupt UART0 receive interrupt SPI interrupt MMC interrupt DMA channel 3 interrupt DMA channel 2 interrupt DMA channel 1 interrupt DMA channel 0 interrupt Reserved for future use UART0/1 error Interrupt Timer4 interrupt Timer3 interrupt Timer2 interrupt Timer1 interrupt Timer0 interrupt Watch-Dog timer interrupt RTC Time tick interrupt External interrupt 7 External interrupt 6 External interrupt 5 External interrupt 4 External interrupt 3 External interrupt 2 External interrupt 1 External interrupt 0 Arbiter Group ARB5 ARB5 ARB5 ARB5 ARB4 ARB4 ARB4 ARB4 ARB4 ARB4 ARB 3 ARB3 ARB3 ARB3 ARB3 ARB3 ARB2 ARB2 ARB2 ARB2 ARB 2 ARB2 ARB1 ARB1 ARB1 ARB1 ARB1 ARB1 ARB0 ARB0 ARB0 ARB0
14-3
INTERRUPT CONTROLLER
S3C2400 RISC MICROPROCESSOR
INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and one second-level arbiter as shown in the following figure.
ARM IRQ
ARBITER6
REQ0 REQ1 REQ2 REQ3 REQ4 REQ5
ARBITER0
REQ1/EINT0 REQ2/EINT1 REQ3/EINT2 REQ4/EINT3
ARBITER1
REQ0/EINT4 REQ1/EINT5 REQ2/EINT6 REQ3/EINT7 REQ4/INT_TICK REQ5/INT_WDT REQ0/INT_TIMER0 REQ1/INT_TIMER1 REQ2/INT_TIMER2 REQ3/INT_TIMER3 REQ4/INT_TIMER4 REQ5/INT_UERR0/1 REQ0/Reserved REQ1/INT_DMA0 REQ2/INT_DMA1 REQ3/INT_DMA2 REQ4/INT_DMA3 REQ5/INT_MMC REQ0/INT_SPI REQ1/INT_URXD0 REQ2/INT_URXD1 REQ3/INT_USBD REQ4/INT_USBH REQ5/INT_IIC REQ1/INT_UTXD0 REQ2/INT_UTXD1 REQ3/INT_RTC REQ4/INT_ADC
ARBITER2
ARBITER3
ARBITER4
ARBITER5
Figure 14-1. Priority Generating Block
14-4
S3C2400 RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTERRUPT PRIORITY Each arbiter can handle six interrupt requests based on the one bit arbiter mode control(ARB_MODE) and two bits of selection control signals(ARB_SEL) as follows: If ARB_SEL bits are 00b, the priority order is REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5. If ARB_SEL bits are 01b, the priority order is REQ0, REQ2, REQ3, REQ4, REQ1, and REQ5. If ARB_SEL bits are 10b, the priority order is REQ0, REQ3, REQ4, REQ1, REQ2, and REQ5. If ARB_SEL bits are 11b, the priority order is REQ0, REQ4, REQ1, REQ2, REQ3, and REQ5. Note that REQ0 of an arbiter is always the highest priority, and REQ5 is the lowest one. In addition, by changing the ARB_SEL bits, we can rotate the priority of REQ1 - REQ4. Here, if ARB_MODE bit is set to 0, ARB_SEL bits are not automatically changed, thus the arbiter operates in the fixed priority mode. (Note that even in this mode, we can change the priority by manually changing the ARB_SEL bits.). On the other hand, if ARB_MODE bit is 1, ARB_SEL bits are changed in rotation fashion, e.g., if REQ1 is serviced, ARB_SEL bits are changed to 01b automatically so as to make REQ1 the lowest priority one. The detailed rule of ARB_SEL change is as follows. If REQ0 or REQ5 is serviced, ARB_SEL bits are not changed at all. If REQ1 is serviced, ARB_SEL bits are changed to 01b. If REQ2 is serviced, ARB_SEL bits are changed to 10b. If REQ3 is serviced, ARB_SEL bits are changed to 11b. If REQ4 is serviced, ARB_SEL bits are changed to 00b.
14-5
INTERRUPT CONTROLLER
S3C2400 RISC MICROPROCESSOR
INTERRUPT CONTROLLER SPECIAL REGISTERS
There are five control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, and interrupt pending register. All the interrupt requests from the interrupt sources are first registered in the source pending register. They are divided into two groups based on the interrupt mode register, i.e., one FIQ request and the remaining IRQ requests. Arbitration process is performed for the multiple IRQ requests based on the priority register. SOURCE PENDING REGISTER (SRCPND) SRCPND register is composed of 32 bits each of which is related to an interrupt source. Each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced. By reading this register, we can see the interrupt sources waiting for their requests to be serviced. Note that each bit of SRCPND register is automatically set by the interrupt sources regardless of the masking bits in the INTMASK register. In addition, it is not affected by the priority logic of interrupt controller. In the interrupt service routine for a specific interrupt source, the corresponding bit of SRCPND register has to be cleared to get the interrupt request from the same source correctly. If you return from the ISR without clearing the bit, interrupt controller operates as if another interrupt request comes in from the same source. In other words, if a specific bit of SRCPND register is set to 1, it is always considered as a valid interrupt request waiting to be serviced. The specific time to clear the corresponding bit depends on the user's requirement. The bottom line is that if you want to receive another valid request from the same source you should clear the corresponding bit first, and then enable the interrupt. You can clear a specific bit of SRCPND register by writing a data to this register. It clears only the bit positions of SRCPND corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are with no change Register SRCPND Address 0X14400000 R/W R/W Description Indicates the interrupt request status. 0 = The interrupt has not been requested. 1 = The interrupt source has asserted the interrupt request.
NOTE: When the user clear a interrupt pending, specific bit of SRCPND and INTPND, has to clear the bit of SRCPND.
Reset Value 0x00000000
14-6
S3C2400 RISC MICROPROCESSOR
INTERRUPT CONTROLLER
SRCPND INT_ADC INT_RTC INT_UTXD1 INT_UTXD0 INT_IIC INT_USBH INT_USBD INT_URXD1 INT_URXD0 INT_SPI INT_MMC INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 Reserved INT_UERR0/1 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0
Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, Not used 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested,
Description 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested
Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.
14-7
INTERRUPT CONTROLLER
S3C2400 RISC MICROPROCESSOR
INTERRUPT MODE REGISTER (INTMOD) This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode. Otherwise, it is processed in the IRQ mode (normal interrupt). Note that at most only one interrupt source can be serviced in the FIQ mode in the interrupt controller. (You should use the FIQ mode only for the urgent interrupt.) Thus, only one bit of INTMOD can be set to 1 at most. This register is write-only one, thus it cannot be read out. Register INTMOD Address 0X14400004 R/W W Description Interrupt mode register. 0 = IRQ mode
NOTE:
Reset Value 0x00000000
1 = FIQ mode
If an interrupt mode is set to FIQ mode in INTMOD register, FIQ interrupt will not affect INTPND and INTOFFSET registers. The INTPND and INTOFFSET registers are valid only for IRQ mode interrupt source.
14-8
S3C2400 RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTMOD INT_ADC INT_RTC INT_UTXD1 INT_UTXD0 INT_IIC INT_USBH INT_USBD INT_URXD1 INT_URXD0 INT_SPI INT_MMC INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 Reserved INT_UERR0/1 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0
Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
Description 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ
Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Not used 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ
14-9
INTERRUPT CONTROLLER
S3C2400 RISC MICROPROCESSOR
INTERRUPT MASK REGISTER (INTMSK) Each of the 32 bits in the interrupt mask register is related to an interrupt source. If you set a specific bit to 1, the interrupt request from the corresponding interrupt source is not serviced by the CPU. (Note that even in such a case, the corresponding bit of SRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced. Register INTMSK Address 0X14400008 R/W R/W Description Determines which interrupt source is masked. The masked interrupt source will not be serviced. 0 = Interrupt service is available 1 = Interrupt service is masked Reset Value 0xffffffff
14-10
S3C2400 RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTMSK INT_ADC INT_RTC INT_UTXD1 INT_UTXD0 INT_IIC INT_USBH INT_USBD INT_URXD1 INT_URXD0 INT_SPI INT_MMC INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 Reserved INT_UERR0/1 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0
Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
Description 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, Not used 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked
Initial State 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
14-11
INTERRUPT CONTROLLER
S3C2400 RISC MICROPROCESSOR
PRIORITY REGISTER (PRIORITY) Register PRIORITY Address 0X1440000C R/W W Description IRQ priority control register Reset Value 0x7f
PRIORITY ARB_SEL6
Bit [20:19]
Description Arbiter 6 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 5 group priority order set 00 = REQ 1-2-3-4 01 = REQ 2-3-4-1 10 = REQ 3-4-1-2 11 = REQ 4-1-2-3 Arbiter 4 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 3 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 2 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 1 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 0 group priority order set 00 = REQ 1-2-3-4 01 = REQ 2-3-4-1 10 = REQ 3-4-1-2 11 = REQ 4-1-2-3 Arbiter 6 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 5 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 4 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 3 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 2 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 1 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 0 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable
Initial State 0
ARB_SEL5
[18:17]
0
ARB_SEL4
[16:15]
0
ARB_SEL3
[14:13]
0
ARB_SEL2
[12:11]
0
ARB_SEL1
[10:9]
0
ARB_SEL0
[8:7]
0
ARB_MODE6 ARB_MODE5 ARB_MODE4 ARB_MODE3 ARB_MODE2 ARB_MODE1 ARB_MODE0
[6] [5] [4] [3] [2] [1] [0]
1 1 1 1 1 1 1
14-12
S3C2400 RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTERRUPT PENDING REGISTER (INTPND) Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request is the highest priority one that is unmasked and waits for the interrupt to be serviced. Since INTPND is located after the priority logic, only one bit can be set to 1 at most, and that is the very interrupt request generating IRQ to CPU. In interrupt service routine for IRQ, you can read this register to determine the interrupt source to be serviced among 32 sources. Like the SRCPND, this register has to be cleared in the interrupt service routine after clearing SRCPND register. We can clear a specific bit of INTPND register by writing a data to this register. It clears only the bit positions of INTPND corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are with no change. Register INTPND Address 0X14400010 R/W R/W Description Indicates the interrupt request status. 0 = The interrupt has not been requested 1 = The interrupt source has asserted the interrupt request
NOTE: If the FIQ mode interrupt is occurred, the corresponding bit of INTPND will not be turned on. Because the INTPND register is available only for IRQ mode interrupt.
Reset Value 0x00000000
14-13
S3C2400 RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTPND INT_ADC INT_RTC INT_UTXD1 INT_UTXD0 INT_IIC INT_USBH INT_USBD INT_URXD1 INT_URXD0 INT_SPI INT_MMC INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 Reserved INT_UERR0/1 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0
Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, Not used 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested,
Description 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested
Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14-14
S3C2400 RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTERRUPT OFFSET REGISTER (INTOFFSET) The number in the interrupt offset register shows which interrupt request of IRQ mode is in the INTPND register. This bit can be cleared automatically by clearing SRCPND and INTPND. Register INTOFFSET Address 0X14400014 R/W R Description Indicates the IRQ interrupt request source Reset Value 0x00000000
INT Source INT_ADC INT_RTC INT_UTXD1 INT_UTXD0 INT_IIC INT_USBH INT_USBD INT_URXD1 INT_URXD0 INT_SPI INT_MMC INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 Reserved
NOTE:
The OFFSET value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT Source INT_UERR0/1 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0
The OFFSET value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
If the FIQ mode interrupt is occurred, the INTOFFSET will not be affected. Because the INTOFFSET register is available only for IRQ mode interrupt.
14-15
INTERRUPT CONTROLLER
S3C2400 RISC MICROPROCESSOR
NOTES
14-16
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
15
OVERVIEW
LCD CONTROLLER
The LCD controller within S3C2400X01 consists of logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver. The LCD controller supports monochrome, 2-bit per pixel (4-level gray scale) or 4-bit per pixel (16-level gray scale) mode on a monochrome LCD, using a time-based dithering algorithm and FRC (Frame Rate Control) method and it can be interfaced with a color LCD panel at 8-bit per pixel (256-level color) and 12-bit per pixel (4096-level color) for interfacing with STN LCD. It can support 1-bit per pixel, 2-bit per pixel, 4-bit per pixel, 8-bit per pixel for interfacing with the palettized TFT color LCD panel and 16 non-palettized true-color display. The LCD controller can be programmed to support the different requirements on the screen related to the number of horizontal and vertical pixels, data line width for the data interface, interface timing, and refresh rate.
FEATURES STN LCD Displays Features -- Supports 3 types of LCD panels: 4-bit dual scan, 4-bit single scan, 8-bit single scan display type. -- Supports the monochrome, 4 gray levels, and 16 gray levels . -- Supports 256 level colors and 4096 level colors for color STN LCD panel. -- Supports multiple screen size. Typical actual screen sizes: 320x240, 160x160 (pixels) Maximum virtual screen sizes(color mode): 4096x1024, 2048x2048, 1024x4096, etc TFT LCD Displays Features -- Supports 1, 2, 4 or 8 bpp (bit per pixel) palettized color displays for TFT. -- Supports 16 non-palettized true-color displays for color TFT. -- Supports maximum 64K color TFT at 16-bit per pixel mode. -- Supports multiple screen size. Typical actual screen size: 720x240, 320x240, 160x160 (pixels) Maximum virtual screen size (16 bpp mode): 2048x1024 etc
15-1
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
Common features -- Dedicated DMA supports to fetch the image data from video buffer located in system memory. -- Supports power saving mode. -- The system memory is used as the display memory. -- Supports Multiple Virtual Display Screen. (Supports Hardware Horizontal/Vertical Scrolling) -- Programmable timing control for different display panels. -- Supports little and big-endian byte ordering, as well as WinCE data formats. EXTERNAL INTERFACE SIGNAL VFRAME / VSYNC: VLINE / HSYNC: VCLK: VD[15:0]: VM / VDEN: LEND: * Frame synchronous signal (STN) / Vertical synchronous signal (TFT). Line synchronous pulse signal (STN) / Horizontal synchronous signal (TFT) Pixel clock signal (STN/TFT) LCD pixel data output ports (STN/TFT) AC bias signal for the STN LCD driver (STN) / Data enable signal (TFT) Line end signal (TFT)
Total 21 output ports, data 16 bits, control 5 bits
15-2
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
BLOCK DIAGRAM
System Bus
REGBANK
TIMEGEN
VCLK VLINE VFRAME VM . . . .
LCDCDMA
VIDPRCS
VD[15:0]
Figure 15-1. LCD Controller Block Diagram The LCD controller within S3C2400 is used to transfer the video data and to generate the necessary control signals such as, VFRAME, VLINE, VCLK, VM and so on. As well as the control signals, S3C2400has the data ports of video data, which are VD[15:0] as shown in Figure 15-1. The LCD controller consists of a REGBANK, LCDCDMA, VIDPRCS, and TIMEGEN (See Figure 15-1 LCD Controller Block Diagram). The REGBANK has 21 programmable register sets and 256x16 palette memory which are used to configure the LCD controller. The LCDCDMA is a dedicated DMA, which it can transfer the video data in frame memory to LCD driver, automatically. By using this special DMA, the video data can be displayed on the screen without CPU intervention. The VIDPRCS receives the video data from LCDCDMA and sends the video data through the VD[15:0] data ports to the LCD driver after changing them into a suitable data format, for example 4/8-bit single scan or 4-bit dual scan display mode. The TIMEGEN consists of programmable logic to support the variable requirement of interface timing and rates commonly found in different LCD drivers. The TIMEGEN block generates VFRAME, VLINE, VCLK, VM, and so on. The description of data flow is as follows: FIFO memory is present in the LCDCDMA. When FIFO is empty or partially empty, LCDCDMA requests data fetching from the frame memory based on the burst memory transfer mode(Consecutive memory fetching of 4 words(16 bytes) per one burst request without allowing the bus mastership to another bus master during the bus transfer). When this kind of transfer request is accepted by bus arbitrator in the memory controller, there will be four successive word data transfers from system memory to internal FIFO. The total size of FIFO is 24 words, which consists of FIFOL and FIFOH of 12 words, respectively. The S3C2400 has two FIFOs because it needs to support the dual scan display mode. In case of single scan mode, one of them can only be used.
15-3
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER OPERATION (STN CASE)
TIMING GENERATOR The TIMEGEN generates the control signals for LCD driver such as, VFRAME, VLINE, VCLK, and VM. These control signals are closely related to the configuration on the LCDCON1/2/3/4/5 register in the REGBANK. Based on these programmable configurations on the LCD control registers in REGBANK, the TIMEGEN can generate the programmable control signals suitable to support many different types of LCD drivers. The VFRAME pulse is asserted for a duration of the entire first line at a frequency of once per frame. The VFRAME signal is asserted to bring the LCD's line pointer to the top of the display to start over. The VM signal is used by the LCD driver to alternate the polarity of the row and column voltage used to turn the pixel on and off. The toggle rate of VM signal can be controlled by using the MMODE bit of LCDCON 1 register and MVAL field of LCDCON4 register. If the MMODE bit is 0, the VM signal is configured to toggle on every frame. If the MMODE bit is 1, the VM signal is configured to toggle on the every event of the elapse of the specified number of VLINE by the MVAL[7:0] value. Figure 15-5 shows an example for MMODE=0 and for MMODE=1 with the value of MVAL[7:0]=0x2. When MMODE=1, the VM rate is related to MVAL[7:0], as shown below: VM Rate = VLINE Rate / ( 2 x MVAL) The VFRAME and VLINE pulse generation is controlled by the configurations of the HOZVAL field and the LINEVAL field in the LCDCON2/3 register. Each field is related to the LCD size and display mode. In other words, the HOZVAL and LINEVAL can be determined by the size of the LCD panel and the display mode according to the following equation: HOZVAL = (Horizontal display size / Number of the valid VD data line) -1 In color mode: Horizontal display size = 3 x Number of Horizontal Pixel In the 4-bit single scan display mode, number of valid VD data lines should be 4. In case of 4-bit dual scan display the number of valid VD data lines should be 4 and in case of 8-bit single scan display mode, the number of valid VD data lines should be 8.
LINEVAL = (Vertical display size) -1: In case of single scan display type LINEVAL = (Vertical display size / 2) -1: In case of dual scan display type The rate of VCLK signal can be controlled by the CLKVAL field in the LCDCON1 register. The Table 15-1 defines the relationship of VCLK and CLKVAL. The minimum value of CLKVAL is 2. VCLK(Hz)=HCLK/(CLKVAL x 2) The frame rate is the VFRAM signal frequency. The frame rate is closely related to the field of WLH[1:0](VLINE pulse width) WDLY[1:0](the delay width of VCLK after VLINE pulse), HOZVAL, LINEBLANK, and LINEVAL in LCDCON1 and LCDCON2/3/4 registers as well as VCLK and HCLK. Most LCD drivers need their own adequate frame rate. The frame rate is calculated as follows; frame_rate(Hz) = 1 / [((1/VCLK) x (HOZVAL+1)+(1/HCLK) x (WLH+WDLY+(LINEBLANK x 8) ) ) x (LINEVAL+1)] VCLK(Hz) = (HOZVAL+1) / [(1 /(frame_rate x (LINEVAL+1))) - ((WLH+WDLY+(LINEBLANK x 8) ) / HCLK )]
15-4
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
Table 15-1. Relation between VCLK and CLKVAL(STN, HCLK=60MHz) CLKVAL 2 3
* * *
60MHz/X 60 MHz/4 60 MHz/6
* * *
VCLK 15.0 MHz 10.0 MHz
* * *
1023
60 MHz/2046
29.3 kHz
VIDEO OPERATION The LCD controller within S3C2400 supports 8-bit color mode (256 color mode), 12-bit color mode (4096 color mode), 4 level gray scale mode, 16 level gray scale mode as well as the monochrome mode. When the gray or color mode is needed, the implementation of the shades of gray level or color should be followed by time-based dithering algorithm and FRC(Frame Rate Control) method can be used to implement the shades of gray or color from which selection can be made by using a programmable lockup table, which will be explained later. The monochrome mode bypasses these modules(FRC and lookup table) and basically serializes the data in FIFOH (and FIFOL if a dual scan display type is used) into 4-bit (or 8-bit if a 4-bit dual scan or 8-bit single scan display type is used) streams by shifting the video data to the LCD driver. The following sections describe the operation on gray mode and color mode in terms of the lookup table and FRC. Lookup Table The S3C2400 can support the palette table for various selection of color or gray level mapping. This kind of selection gives users flexibility. The lookup table is the palette which allows the selection on the level of color or gray(Selection on 4-gray levels among 16 gray levels in case of gray mode, selection on 8 red levels among 16 levels, 8 green levels among 16 levels and 4 blue levels among 16 levels in case of color mode). In other words, users can select 4 gray levels among 16 gray levels by using the lookup table in the 4 gray level mode. The gray levels cannot be selected in the 16 gray level mode; all 16 gray levels must be chosen among the possible 16 gray levels. In case of 256 color mode, 3 bits are allocated for red, 3 bits for green and 2 bits for blue. The 256 colors mean that the colors are formed from the combination of 8 red, 8 green and 4 blue levels(8x8x4 = 256). In the color mode, the lookup table can be used for suitable selections. Eight red levels can be selected among 16 possible red levels, 8 green levels among 16 green levels, and 4 blue levels among 16 blue levels. In case of 4096 color mode, of course there is no selection as in the 256 color mode. Gray Mode Operation Two gray modes are supported by the LCD controller within the S3C2400: 2-bit per pixel gray (4 level gray scale) or 4-bit per pixel gray (16 level gray scale). The 2-bit per pixel gray mode uses a lookup table, which allows selection on 4 gray levels among 16 possible gray levels. The 2-bit per pixel gray lookup table uses the BULEVAL[15:0] in BLUELUT(Blue Lookup Table) register as same as blue lookup table in color mode. The gray level 0 will be denoted by BLUEVAL[3:0] value. If BLUEVAL[3:0] is 9, level 0 will be represented by gray level 9 among 16 gray levels. If BLUEVAL[3:0] is 15, level 0 will be represented by gray level 15 among 16 gray levels, and so on. As same as in the case of level 0, level 1 will also be denoted by BLUEVAL[7:4], the level 2 by BLUEVAL[11:8], and the level 3 by BLUEVAL[15:12]. These four groups among BLUEVAL[15:0] will represent level 0, level 1, level 2, and level 3. In 16 gray levels, of course there is no selection as in the 4 gray levels.
15-5
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
256 Level Color Mode Operation The LCD controller in S3C2400 can support an 8-bit per pixel 256 color display mode. The color display mode can generate 256 levels of color using the dithering algorithm and FRC. The 8-bit per pixel are encoded into 3-bits for red, 3-bits for green, and 2-bits for blue. The color display mode uses separate lookup tables for red, green, and blue. Each lookup table uses the REDVAL[31:0] of REDLUT register, GREENVAL[31:0] of GREENLUT register, and BLUEVAL[15:0] of BLUELUT register as the programmable lookup table entries. Similarly with the gray level display, 8 group or field of 4 bits in the REDLUR register, i.e., REDVAL[31:28], REDLUT[27:24], REDLUT[23:20], REDLUT[19:16], REDLUT[15:12], REDLUT[11:8], REDLUT[7:4], and REDLUT[3:0], are assigned to each red level. The possible combination of 4 bits(each field) is 16, and each red level should be assigned to one level among possible 16 cases. In other words, the user can select the suitable red level by using this type of lookup table. For green color, the GREENVAL[31:0] of the GREENLUT register is assigned as the lookup table, as was done in the case of red color. Similarly, the BLUEVAL[15:0] of the BLUELUT register is also assigned as a lookup table. For blue color, we need 16bit for a lookup table because 2 bits are allocated for 4 blue levels, different from the 8 red or green levels. 4096 Level Color Mode Operation The LCD controller in S3C2400can support an 12-bit per pixel 4096 color display mode. The color display mode can generate 4096 levels of color using the dithering algorithm and FRC. The 12-bit per pixel are encoded into 4-bits for red, 4-bits for green, and 4-bits for blue. The color display mode does not use lookup tables.
15-6
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
DITHERING AND FRC (FRAME RATE CONTROL) For STN LCD displays(except monochrome), video data must be processed by a dithering algorithm. The DITHFRC block has two functions, such as a Time-based Dithering Algorithm for reducing flicker and FRC(Frame Rate Control) for displaying gray and color level on the STN panel. The main principle of gray and color level display on the STN panel based on FRC is described. For example, to display the third gray (3/16) level from a total of 16 levels, the 3 times pixel should be on and 13 times pixel off. In other words, 3 frames should be selected among the 16 frames, of which 3 frames should have a pixel-on on a specific pixel while the remaining 13 frames should have a pixel-off on a specific pixel. These 16 frames should be displayed periodically. This is basic principle on how to display the gray level on the screen, so-called gray level display by FRC(Frame Rate Control). The actual example is shown in Table 15-2. To represent the 14th gray level in the table, we should have a 6/7 duty cycle, which mean that there are 6 times pixel-on and one time pixel-off. The other cases for all gray levels are also shown in Table 15-2. In the STN LCD display, we should be reminded of one item, i.e., Flicker Noise due to the simultaneous pixel-on and -off on adjacent frames. For example, if all pixels on first frame are turned on and all pixels on next frame are turned off, the Flicker Noise will be maximized. To reduce the Flicker Noise on the screen, the average probability of pixelon and -off between frames should be as same as possible. In order to realize this, the Time-based Dithering Algorithm, which varies the pattern of adjacent pixels on every frame, should be used. This is explained in detail. For the 16 gray level, FRC should have the following relationship between gray level and FRC. The 15th gray level should always have pixel-on, and the 14th gray level should have 6 times pixel-on and one times pixel-off, and the 13th gray level should have 4 times pixel-on and one times pixel-off, ,,,,,,,, , and the 0th gray level should always have pixel-off as shown in Table 15-2. Table 15-2. Dither Duty Cycle Examples Pre-dithered Data (gray level number) 15 14 13 12 11 10 9 8 1 6/7 4/5 3/4 5/7 2/3 3/5 4/7 Duty Cycle Pre-dithered Data (gray level number) 7 6 5 4 3 2 1 0 1/2 3/7 2/5 1/3 1/4 1/5 1/7 0 Duty Cycle
15-7
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
Display Types The LCD controller supports 3 types of LCD drivers: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display mode. Figure 15-3 shows these 3 different display types for monochrome displays, and Figure 15-4 show these 3 different display types for color displays. 4-bit Dual Scan Display Type A 4-bit dual scan display uses 8 parallel data lines to shift data to both the upper and lower halves of the display at the same time. The 4 bits of data in the 8 parallel data lines are shifted to the upper half and 4 bits of data is shifted to the lower half, as shown in Figure 15-3. The end of frame is reached when each half of the display has been shifted and transferred. The 8 pins (VD[7:0]) for the LCD output from the LCD controller can be directly connected to the LCD driver. 4-bit Single Scan Display Type A 4-bit single scan display uses 4 parallel data lines to shift data to successive single horizontal lines of the display at a time, until the entire frame has been shifted and transferred. The 4 pins(VD[3:0]) for the LCD output from the LCD controller can be directly connected to the LCD driver, and the 4 pins(VD[7:4]) for the LCD output are not used. 8-bit Single Scan Display Type An 8-bit single scan display uses 8 parallel data lines to shift data to successive single horizontal lines of the display at a time, until the entire frame has been shifted and transferred. The 8 pins (VD[7:0]) for the LCD output from the LCD controller can be directly connected to the LCD driver. 256 Color Displays Color displays require 3 bits (Red, Green, Blue) of image data per pixel, resulting in a horizontal shift register of length 3 times the number of pixels per horizontal line. This RGB is shifted to the LCD driver as consecutive bits via the parallel data lines. Figure 15-4 shows the RGB and order of the pixels in the parallel data lines for the 3 types of color displays. 4096 Color Displays Color displays require 3 bits (Red, Green, Blue) of image data per pixel, resulting in a horizontal shift register of length 3 times the number of pixels per horizontal line. This RGB is shifted to the LCD driver as consecutive bits via the parallel data lines. This RGB order is determined by the sequence of video data in video buffers.
15-8
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
MEMORY DATA FORMAT (STN, BSWP=0) Mono 4-bit Dual Scan Display: Video Buffer Memory: Address 0000H 0004H
* * *
LCD Panel A[31] A[30] ...... A[0] B[31] B[30] ...... B[0] ......
Data A[31:0] B[31:0]
L[31] L[30] ...... L[0] M[31] M[30] ...... M[0] ......
1000H 1004H
* * *
L[31:0] M[31:0]
LCD Panel
Mono 4-bit Single Scan Display & 8-bit Single Scan Display: Video Buffer Memory: Address 0000H 0004H 0008H
* * *
A[31] A[30] A[29] ...... A[0] B[31] B[30] ...... B[0] C[31] ...... C[0] ......
Data A[31:0] B[31:0] C[31:0]
15-9
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
In 4-level gray mode, 2 bits of video data correspond to 1 pixel. In 16-level gray mode, 4 bits of video data correspond to 1 pixel. In 256 level color mode, 8 bits (3 bits of red, 3 bits of green, 2 bits of blue) of video data correspond to 1 pixel. The color data format in a byte is as follows; Bit [ 7:5 ] Red Bit [ 4:2 ] Green Bit[1:0] Blue
In 4096 level color mode, 12 bits (4 bits of red, 4 bits of green, 4 bits of blue) of video data correspond to 1 pixel. The color data format in words is as follows; ( Video data must be reside at 3 word boundaries ( 8 pixel), as follows) RGB order DATA Word #1 Word #2 Word #3 [31:28] Red( 1) Blue(3) Green(6) [27:24] Green(1) Red(4) Blue(6) [23:20] Blue( 1) Green(4) Red(7) [19:16] Red( 2) Blue(4) Green(7) [15:12] Green( 2) Red(5) Blue(7) [11:8] Blue( 2) Green(5) Red(8) [7:4] Red(3) Blue(5) Green(8) [3:0] Green(3) Red(6) Blue(8)
15-10
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
LCD Self Refresh Mode The LCD controller within S3C2400X01 can support the self refresh mode to reduce power comsumption. The self refresh mode can only be applied to only the LCD which has the special LCD driver, for example, LCD panel of SED1580D from Seiko Epson Corporation. The SED1580D has the built-in monochrome display memory, which can display the previous stored image in the built-in monochrome display memory without image data fetch when the self refresh mode has been invoked. But SED1580D has the built-in display memory for monochrome only. So, the user has to set one more frame as a monochrome mode before the entering to self refresh mode. The kind of self refresh mode can be made by writing the control bit of SELFREF in the LCDCON5 register. If the SELFREF bit is set to 1, the LCD controller enters into the self refresh mode from the next line. When the LCD controller enters into the self refresh mode, the signal of VCLK and VD should be fixed as Low and last data value, but the signal of VM, VFRAME, and VLINE will be generated continuously. To exit the self refresh mode, the user should disable SELFREF bit in LCDCON 5 register. SL_IDLE Mode (LCD dedicated Idle Mode) The SL_IDLE mode in the power management scheme should be used to enter into the LCD driver's self refresh mode. In SL_IDLE mode, all function blocks except the LCD controller within S3C2400X01should be stopped to reduce the power comsumption, because the power management block inserts divide_by_n input clock only to the LCD controller. For more information, please refer to the chapter, clock & power management and our example source code. Timing Requirements Image data should be transferred from the memory to the LCD driver using the VD[7:0] signal. VCLK signal is used to clock the data into the LCD driver's shift register. After each horizontal line of data has been shifted into the LCD driver's shift register, the VLINE signal is asserted to display the line on the panel. The VM signal provides an AC signal for the display. It is used by the LCD to alternate the polarity of the row and column voltages, used to turn the pixels on and off, because the LCD plasma tends to deteriorate whenever subjected to a DC voltage. It can be configured to toggle on every frame or to toggle every programmable number of VLINE signals. Figure 15-5 shows the timing requirements for the LCD driver interface.
15-11
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
VD3
VD2
VD1
VD0
VD3
VD2
VD1
VD0
......
VD3
VD2
VD1
VD0
VD3
VD2
VD1
VD0
......
4-bit Dual Scan Display VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 ......
4-bit Single Scan Display VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 ......
8-bit Single Scan Display
Figure 15-2. Monochrome Display Types (STN)
15-12
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
VD3 R1
VD2 G1 1 Pixel
VD1 B1
VD0 R2
VD3 G2
VD2 B2
VD1 R3
VD0 G3
.
.
.
.
.
.
VD7 R1
VD6 G1
VD5 B1
VD4 R2
VD7 G2
VD6 B2
VD5 R3
VD4 G3
.
.
.
.
.
.
4-bit Dual Scan Display
VD3 R1
VD2 G1 1 Pixel
VD1 B1
VD0 R2
VD3 G2
VD2 B2
VD1 R3
VD0 G3
.
.
.
.
.
.
4-bit Single Scan Display
VD7 R1
VD6 G1 1 Pixel
VD5 B1
VD4 R2
VD3 G2
VD2 B2
VD1 R3
VD0 G3
.
.
.
.
.
.
8-bit Single Scan Display
Figure 15-3. Color Display Types (STN)
15-13
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
Full Frame Timing, MMODE = 0 VFRAME VM VLINE LINE1LINE2LINE3LINE4LINE5LINE6 Full Frame Timing, MMODE = 1 VFRAME VM VLINE LINE1LINE2LINE3LINE4LINE5LINE6 LINEnLINE1 LINEnLINE1
First Line Timing VFRAME VM VLINE LINECNT VCLK WDLY First Line Check & Data Timing VFRAME VM VLINE VCLK VD[7:0] WDLY WLH LINEBLANK WDLY Display the last line of the previous frame LINECNT decreases & Display the 1st line
Figure 15-4. 8-bit Single Scan Display Type STN LCD Timing
15-14
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
LCD CONTROLLER OPERATION(TFT CASE)
The TIMEGEN generates the control signals for LCD driver such as, VSYNC, HSYNC, VCLK, VDEN, and LEND signal. These control signals are highly related with the configuration on the LCDCON1/2/3/4/5 registers in the REGBANK. Base on these programmable configuration on the LCD control registers in REGBANK, the TIMEGEN can generate the programmable control signals suitable for the support of many different types of LCD drivers. The VSYNC signal is asserted to cause the LCD's line pointer to start over at the top of the display. The VSYNC and HSYNC pulse generation is controlled by the configuration of both the HOZVAL field and the LINEVAL field in the LCDCON2/3 registers. The HOZVAL and LINEVAL can be determined by the size of the LCD panel according to the following equations: HOZVAL = (Horizontal display size) -1 LINEVAL = (Vertical display size) -1 The rate of VCLK signal can be controlled by the CLKVAL field in the LCDCON1 register. The table below defines the relationship of VCLK and CLKVAL. The minimum value of CLKVAL is 1. VCLK(Hz)=HCLK/[(CLKVAL+1)x2] The frame rate is VSYNC signal frequency. The frame rate is related with the field of VSYNC, VBPD, VFPD, LINEVAL, HSYNC, HBPD, HFPD, HOZVAL, CLKVAL in LCDCON1 and LCDCON2/3/4 registers. Most LCD driver need their own adequate frame rate. The frame rate is calculated as follows; Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } x {(HSPW+1) + (HBPD +1) + (HFPD+1) + (HOZVAL + 1) } x { 2 x ( CLKVAL+1 ) / ( SYSTEM CLK ) } ]
Table 15-3. Relation between VCLK and CLKVAL(TFT, HCLK=60MHz) CLKVAL 1 2 : 1023 60MHz/X 60 MHz/4 60 MHz/6 : 60 MHz/2048 VCLK 15.0 MHz 10.0 MHz : 30.0 kHz
VIDEO OPERATION The TFT LCD controller within S3C2400X01 supports 1, 2, 4 or 8 bpp(bit per pixel) palettized color displays and 16bpp non-palettized true-color displays.
256 Color Palette The S3C2400X01 can support the 256 color palette for various selection of color mapping. This kind of selection can give the flexibility to users
15-15
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
MEMORY DATA FORMAT (TFT) BPP16 Display (BSWP = 0, HWSWP = 0) D[31:16] 000H 004H 008H ... P1 P3 P5 D[15:0] P2 P4 P6
(BSWP = 0, HWSWP = 1) D[31:16] 000H 004H 008H ... P2 P4 P6 D[15:0] P1 P3 P5
P1
P2
P3
P4
P5
......
LCD Panel
15-16
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
BPP8 Display (BSWP = 0, HWSWP = 0) D[31:24] 000H 004H 008H ... P1 P5 P9 D[23:16] P2 P6 P10 D[15:8] P3 P7 P11 D[7:0] P4 P8 P12
(BSWP = 1, HWSWP = 0) D[31:24] 000H 004H 008H ... P4 P8 P12 D[23:16] P3 P7 P11 D[15:8] P2 P6 P10 D[7:0] P1 P5 P9
P1
P2
P3
P4
P5
P6
P7
P8
P9 P10 P11 P12 ......
LCD Panel
15-17
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
BPP4 Display (BSWP = 0, HWSWP = 0) D[31:28] 000H 004H 008H ... P1 P9 P17 D[27:24] P2 P10 P18 D[23:20] P3 P11 P19 D[19:16] P4 P12 P20 D[15:12] P5 P13 P21 D[11:8] P6 P14 P22 D[7:4] P7 P15 P23 D[3:0] P8 P16 P24
(BSWP = 1, HWSWP = 0) D[31:28] 000H 004H 008H ... P7 P15 P23 D[27:24] P8 P16 P24 D[23:20] P5 P13 P21 D[19:16] P6 P14 P22 D[15:12] P3 P11 P19 D[11:8] P4 P12 P20 D[7:4] P1 P9 P17 D[3:0] P2 P10 P18
BPP2 Display (BSWP = 0, HWSWP = 0) D 000H 004H 008H ... [31:30] P1 P17 P33 [29:28] P2 P18 P34 [27:26] P3 P19 P35 [25:24] P4 P20 P36 [23:22] P5 P21 P37 [21:20] P6 P22 P38 [19:18] P7 P23 P39 [17:16] P8 P24 P40
D 000H 004H 008H ...
[15:14] P9 P25 P41
[13:12] P10 P26 P42
[11:10] P11 P27 P43
[9:8] P12 P28 P44
[7:6] P13 P29 P45
[5:4] P14 P30 P46
[3:2] P15 P31 P47
[1:0] P16 P32 P48
15-18
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
256 PALETTE USAGE( TFT ) Palette Configuration S3C2400X01 provides 256 color palette for TFT LCD Control. 256 color palette consist of the 256(depth) x 16-bit SPSRAM. Palette supports 5:6:5(R:G:B) format and 5:5:5:1(R:G:B:I) format. When the user use 5:5:5:1 format, the intensity data(I) is used as a common LSB bit of each RGB data. So, 5:5:5:I format is same as R(5+I):G(5+I):B(5+I) format. For example, R(5+I)=VD[15:11]+VD[0], G(5+1)=VD[10:6]+VD[0], B(5+1)=VD[5:1]+VD[0]. The user can select 256 colors from the 64K colors through these two formats. Table 15-4. 5:6:5 Format INDEX\Bit Pos. 00H 01H ....... FFH R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 Table 15-5. 5:5:5:1 Format INDEX\Bit Pos. 00H 01H ....... FFH R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 I 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I I Address 0X14A00400 0X14A00404 ....... 0X14A007FC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address *0X14A00400 0X14A00404 ....... 0X14A007FC
R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
NOTES: 1. * 0x14A00400 is Palette start address. 2. DATA[31:16] is invalid.
Palette Read/Write When the user going to do Read/Write operation on the palette, VSTATUS of LCDCON5 register must be checked. Because Read/Write operation is prohibited during the ACTIVE status of VSTATUS. Temp Configuration S3C2400X01 supports that the user can fill a frame with one color without complex modification to fill the one color to the video buffer or palette. The one colored frame can be displayed by the writing a value of the color which is displayed on LCD panel to TPALVAL of TPAL register and enable TPALEN. Palette Offset Control The index of Palette can be modified by the offset. This function provides special effect on LCD panel for the user.
15-19
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 R4 B3 B2 B1 B0 I
1
2
3
4
5
LCD Panel
16BPP 5:5:5+1 Format
A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
1
2
3
4
5
LCD Panel
16BPP 5:6:5
Format
Figure 15-5. BPP16 5:6:5 Display Types (TFT)
15-20
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
VSYNC
HSYNC
VDEN
VSPW+1
VBPD+1
LINEVAL+1 1 FRAME
VFPD+1
1 LINE
HSYNC
VCLK
VD
VDEN
LEND
HSPW+1 HBPD+1
HOZVAL+1
HFPD+1
Figure 15-6. TFT LCD Timing Example
15-21
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
VIRTUAL DISPLAY (TFT/STN) The S3C2400X01 supports hardware horizontal or vertical scrolling. If the screen is scrolled, the fields of LCDBASEU and LCDBASEL in LCDSADDR1/2 registers need to be changed(refer to Figure 15-8) but not the values of PAGEWIDTH and OFFSIZE. The size of video buffer in which the image is stored should be larger than LCD panel screen size.
OFFSIZE
PAGEWIDTH
OFFSIZE
This is the data of line 1 of virtual screen. This is the data of line 1 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 10 of virtual screen. LCDBASEU This is the data of line 11 of virtual screen. This is the data of line 11 of virtual screen. View Port (The same size of LCD panel) LINEVAL + 1
LCDBASEL
This is the data of line 1 of virtual screen. This is the data of line 1 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 11 of virtual screen. This is the data of line 11 of virtual screen.
Figure 15-7. Example of Scrolling in Virtual Display (Single Scan)
15-22
. . . . . .
Before Scrolling
After Scrolling
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
LCD CONTROLLER SPECIAL REGISTERS LCD Control 1 Register Register LCDCON1 Address 0X14A00000 R/W R/W Description LCD control 1 register Reset Value 0x00000000
LCDCON1 LINECNT (read only) CLKVAL
Bit [27:18] [17:8]
Description These bits provide the status of the line counter. Down count from LINEVAL to 0 These bits determine the rates of VCLK and CLKVAL[9:0]. STN: VCLK = HCLK / (CLKVAL x 2) ( CLKVAL 2 ) TFT: VCLK = HCLK / [(CLKVAL+1) x 2] ( CLKVAL 1 ) This bit determines the toggle rate of the VM. 0 = Each Frame, 1 = The rate defined by the MVAL These bits select the display mode. 00 = 4-bit dual scan display mode(STN) 01 = 4-bit single scan display mode(STN) 10 = 8-bit single scan display mode(STN) 11 = TFT LCD panel These bits select the BPP ( Bits Per Pixel) mode. 0000 = 1 bpp for STN, Monochrome mode 0001 = 2 bpp for STN, 4-level gray mode 0010 = 4 bpp for STN, 16-level gray mode 0011 = 8 bpp for STN, color mode 0100 = 12 bpp for STN, color mode 1000 = 1 bpp for TFT 1001 = 2 bpp for TFT 1010 = 4 bpp for TFT 1011 = 8 bpp for TFT 1100 = 16 bpp for TFT LCD video output and the logic enable/disable. 0 = Disable the video output and the LCD control signal. 1 = Enable the video output and the LCD control signal.
Initial State 0000000000 0000000000
MMODE PNRMODE
[7] [6:5]
0 00
BPPMODE
[4:1]
0000
ENVID
[0]
0
15-23
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
LCD Control 2 Register Register LCDCON2 Address 0X14A00004 R/W R/W Description LCD control 2 register Reset Value 0x00000000
LCDCON2 VBPD
Bit [31:24]
Description TFT: Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. STN: These bits should be set to zero on STN LCD.
Initial State 0x00
LINEVAL VFPD
[23:14] [13:6]
TFT/STN: These bits determine the vertical size of LCD panel. TFT: Vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period. STN: These bits should be set to zero on STN LCD.
0000000000 00000000
VSPW
[5:0]
TFT: Vertical sync pulse width determines the VSYNC pulse's high level width by counting the number of inactive lines. STN: These bits should be set to zero on STN LCD.
000000
15-24
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
LCD Control 3 Register Register LCDCON3 Address 0X14A00008 R/W R/W Description LCD control 3 register Reset Value 0x00000000
LCDCON3 HBPD (TFT) WDLY (STN)
Bit [25:19]
Description TFT: Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data. STN: WDLY[1:0] bits determine the delay between VLINE and VCLK by counting the number of the HCLK. WDLY[7:2] are reserved. 00 = 16clock, 01 = 32 clock, 10 = 64 clock, 11 = 128 clock
initial state 0000000
HOZVAL
[18:8]
TFT/STN: These bits determine the horizontal size of LCD panel. HOZVAL has to be determined to meet the condition that total bytes of 1 line are 2n bytes. If the x size of LCD is 120 dot in mono mode, x=120 can not be supported because 1 line is consist of 15 bytes. Instead, x=128 in mono mode can be supported because 1 line is consisted of 16 bytes (2n). LCD panel driver will discard the additional 8 dot.
00000000000
HFPD (TFT) LINEBLANK (STN)
[7:0]
TFT: Horizontal front porch is the number of VCLK periods between the end of active data and the rising edge of HSYNC. STN: These bits indicate the blank time in one horizontal line duration time. These bits adjust the rate of the VLINE finely. The unit of LINEBLANK is HCLK X 8. Ex) If the value of LINEBLANK is 10, the blank time is inserted to VCLK during 80 HCLKs.
0X00
15-25
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
LCD Control 4 Register Register LCDCON4 Address 0X14A0000C R/W R/W Description LCD control 4 register Reset Value 0x00000000
LCDCON4 PALADDEN ADDVAL MVAL HSPW(TFT) WLH(STN)
Bit [24] [23:16] [15:8] [7:0]
Description TFT: Palette Index offset enable 0 = Disable 1 = Enable TFT: Palette Index offset value STN: These bit define the rate at which the VM signal will toggle if the MMODE bit is set logic '1'. TFT: Horizontal sync pulse width determines the HSYNC pulse's high level width by counting the number of the VCLK. STN: WLH[1:0] bits determine the VLINE pulse's high level width by counting the number of the HCLK. WLH[7:2] are reserved. 00 = 16clock, 01 = 32 clock, 10 = 64 clock, 11 = 128 clock
initial state 0 0X00 0X00 0X00
15-26
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
LCD Control 5 Register Register LCDCON5 Address 0X14A00010 R/W R/W Description LCD control 5 register Reset Value 0x00000000
LCDCON5 VSTATUS
Bit [20:19]
Description TFT: Vertical Status (Read only) 00 = VSYNC 01 = BACK Porch 10 = ACTIVE 11 = FRONT Porch TFT: Horizontal Status (Read only) 00 = HSYNC 01 = BACK Porch 10 = ACTIVE 11 = FRONT Porch This bit is reserved and the value should be `0'. This bit is reserved for Test mode and the value should be `0'. STN: If SLOWCLKSYNC is 1, the SLOW mode will be entered from NORMAL mode synchronously when current LCD frame is completed. Also, if SLOWCLKSYNC is 1, the Normal mode will be entered from SLOW mode synchronously when current LCD frame is completed. This feature will be used for changing HCLK and SL_IDLE mode. 0 = Disable 1 = Enable STN: LCD self refresh mode enable bit 0 = LCD self refresh mode disable 1 = LCD self refresh mode enable
initial state 00
HSTATUS
[18:17]
00
Reserved Reserved SLOWCLKSYNC
[16] [15] [14]
0 0 0
SELFREF
[13]
0
Reserved Reserved INVVCLK
[12] [11] [10] STN/TFT: This bit controls the polarity of the VCLK active edge. 0 = The video data is fetched at VCLK falling edge 1 = The video data is fetched at VCLK rising edge STN/TFT: This bit indicates the VLINE/HSYNC pulse polarity. 0 = normal 1 = inverted STN/TFT: This bit indicates the VFRAME/VSYNC pulse polarity. 0 = normal 1 = inverted STN/TFT: This bit indicates the VD (video data) pulse polarity. 0 = Normal 1 = VD is inverted.
0 0 0
INVVLINE INVVFRAME
[9] [8]
0 0
INVVD
[7]
0
15-27
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
LCD Control 5 Register (Continued) LCDCON5 INVVDEN Reserved INVENDLINE Reserved ENLEND Bit [6] [5] [4] [3] [2] TFT: LEND output signal enable/disable. 0 = Disable LEND signal 1 = Enable LEND signal STN/TFT: Byte swap control bit 0 = Swap Disable 1 = Swap Enable STN/TFT: Half-Word swap control bit 0 = Swap Disable 1 = Swap Enable TFT: This bit indicates the LEND signal polarity. 0 = normal 1 = inverted Description TFT: This bit indicates the VDEN signal polarity. 0 = normal 1 = inverted initial state 0 0 0 0 0
BSWP HWSWP
[1] [0]
0 0
15-28
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
FRAME BUFFER START ADDRESS 1 REGISTER Register LCDSADDR1 Address 0X14A00014 R/W R/W Description STN/TFT: Frame buffer start address 1 register Reset Value 0x00000000
LCDSADDR1 LCDBANK
Bit [27:21]
Description These bits indicate A[28:22] of the bank location for the video buffer in the system memory. LCDBANK value can not be changed even when moving the view port. LCD frame buffer should be inside aligned 4MB region, which ensures that LCDBANK value will not be changed when moving the view port. So, using the malloc() function the care should be taken. For dual-scan LCD: These bits indicate A[21:1] of the start address of the upper address counter, which is for the upper frame memory of dual scan LCD or the frame memory of single scan LCD. For single-scan LCD: These bits indicate A[21:1] of the start address of the LCD frame buffer.
Initial State 0x00
LCDBASEU
[20:0]
0x000000
FRAME Buffer Start Address 2 Register Register LCDSADDR2 Address 0X14A00018 R/W R/W Description STN/TFT: Frame buffer start address 2 register Reset Value 0x00000000
LCDSADDR2 LCDBASEL
Bit [20:0]
Description For dual-scan LCD: These bits indicate A[21:1] of the start address of the lower address counter, which is used for the lower frame memory of dual scan LCD. For single scan LCD: These bits indicate A[21:1] of the end address of the LCD frame buffer. LCDBASEL = ((the fame end address) >>1) + 1 = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1)
Initial State 0x0000
NOTE: users
Users can change the LCDBASEU and LCDBASEL values for scrolling while LCD controller is turned on. But, must not change the LCDBASEU and LCDBASEL registers at the end of FRAME by referring to the LINECNT field in LCDCON1 register. Because of the LCD FIFO fetches the next frame data prior to the change in the frame. So, if you change the frame, the pre-fetched FIFO data will be obsolete and LCD controller will display the incorrect screen. To check the LINECNT, interrutpt should be masked. If any interrupt is executed just after reading LINECNT, the read LINECNT value may be obsolete because of the execution time of ISR(interrupt service routine).
15-29
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
FRAME Buffer Start Address 3 Register Register LCDSADDR3 Address 0X14A0001C R/W R/W Description STN/TFT: Virtual screen address set Reset Value 0x00000000
LCDSADDR3 OFFSIZE
Bit [21:11]
Description Virtual screen offset size(the number of half words) This value defines the difference between the address of the last half word displayed on the previous LCD line and the address of the first half word to be displayed in the new LCD line. Virtual screen page width(the number of half words) This value defines the width of the view port in the frame
Initial State 00000000000
PAGEWIDTH
NOTE:
[10:0]
000000000
The values of PAGEWIDTH and OFFSIZE must be changed when ENVID bit is 0.
Example 1. LCD panel = 320*240, 16gray, single scan frame start address = 0xc500000 offset dot number = 2048 dots ( 512 half words ) LINEVAL = 240-1 = 0xef PAGEWIDTH = 320*4/16 = 0x50 OFFSIZE = 512 = 0x200 LCDBANK = 0xc500000 >> 22 = 0x31 LCDBASEU = 0x100000 >> 1 = 0x80000 LCDBASEL = 0x80000 + ( 0x50 + 0x200 ) * ( 0xef + 1 ) = 0xa2b00 Example 2. LCD panel = 320*240, 16gray, dual scan frame start address = 0xc500000 offset dot number = 2048 dots ( 512 half words ) LINEVAL = 120-1 = 0x77 PAGEWIDTH = 320*4/16 = 0x50 OFFSIZE = 512 = 0x200 LCDBANK = 0xc500000 >> 22 = 0x31 LCDBASEU = 0x100000 >> 1 = 0x80000 LCDBASEL = 0x80000 + ( 0x50 + 0x200 ) * ( 0x77 + 1 ) = 0x91580 Example 3. LCD panel = 320*240, color, single scan frame start address = 0xc500000 offset dot number = 1024 dots ( 512 half words ) LINEVAL = 240-1 = 0xef PAGEWIDTH = 320*8/16 = 0xa0 OFFSIZE = 512 = 0x200 LCDBANK = 0xc500000 >> 22 = 0x31 LCDBASEU = 0x100000 >> 1 = 0x80000 LCDBASEL = 0x80000 + ( 0xa0 + 0x200 ) * ( 0xef + 1 ) = 0xa7600
15-30
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
RED Lookup Table Register Register REDLUT Address 0X14A00020 R/W R/W Description STN:Red lookup table register Reset Value 0x00000000
REDLUT REDVAL
Bit [31:0]
Description These bits define which of the 16 shades each of the 8 possible red combinations will choose. 000 010 100 110 = = = = REDVAL[3:0], REDVAL[11:8], REDVAL[19:16], REDVAL[27:24], 001 = REDVAL[7:4] 011 = REDVAL[15:12] 101 = REDVAL[23:20] 111 = REDVAL[31:28]
Initial State 0x00000000
GREEN Lookup Table Register Register GREENLUT Address 0X14A00024 R/W R/W Description STN:Green lookup table register Reset Value 0x00000000
GREENLUT GREENVAL
Bit [31:0]
Description These bits define which of the 16 shades each of the 8 possible green combinations will choose. 000 010 100 110 = = = = GREENVAL[3:0], GREENVAL[11:8], GREENVAL[19:16], GREENVAL[27:24], 001 = GREENVAL[7:4] 011 = GREENVAL[15:12] 101 = GREENVAL[23:20] 111 = GREENVAL[31:28]
Initial State 0x00000000
BLUE Lookup Table Register Register BLUELUT Address 0X14A00028 R/W R/W Description STN:Blue lookup table register Reset Value 0x0000
BULELUT BLUEVAL
Bit [15:0]
Description These bits define which of the 16 shades each of the 4 possible blue combinations will choose 00 = BLUEVAL[3:0], 10 = BLUEVAL[11:8], 01 = BLUEVAL[7:4] 11 = BLUEVAL[15:12]
Initial State 0x0000
NOTE:
Address from 0x14A0002C to 0x14A00048 should not be used. This area is reserved for Test mode.
15-31
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
Dithering Mode Register Register DITHMODE Address 0X14A0004C R/W R/W Description STN:Dithering Mode Register. This register reset value is 0x00000 But, user can change this value to 0x12210. ( Please, refer to a sample program source for the latest value of this register ). Reset Value 0x00000
DITHMODE DITHMODE
Bit [18:0]
Description Use one of following value for your LCD 0x00000 or 0x12210
initial state 0x00000
15-32
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
Temp Palette Register Register TPAL Address 0X14A00050 R/W R/W Description TFT:Temporary Palette Register. This register value will be video data at next frame Reset Value 0x00000000
DITHMODE TPALEN TPALVAL
Bit [16] [15:0]
Description Temporary Palette Register enable bit 0 = Disable 1 = Enable Temporary Palette Value Register. 5:6:5 format: TPALVAL[15:11] : RED TPALVAL[10:5] : GREEN TPALVAL[4:0] : BLUE RED : GREEN : BLUE : Intensity
initial state 0 0x000000
5:5:5:1 format: TPALVAL[15:11] : TPALVAL[10:6] TPALVAL[5:1] TPALVAL[1]
15-33
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
Register Setting Guide (STN) The maximum VCLK frequency of the LCD controller is 16.5MHz whenever HCLK frequency is 66 MHz; therefore the LCD controller supports all existing LCD drivers. The LCD controller supports multiple screen sizes by special register setting. The CLKVAL value determines the frequency of VCLK. The data transmission rate for the VD port of the LCD controller should be calculated, in order to determine the value of CLKVAL register. The data transmission rate is given by the following equation: CLKVAL has to be determined, such that the VCLK value is greater than the data transmission rate. Data transmission rate = HS x VS x FR x MV HS: Horizontal LCD size VS: Vertical LCD size FR: Frame rate MV: Mode dependent value Table 15-6. MV Value for Each Display Mode Mode Mono, 4-bit single scan display Mono, 8-bit single scan display or 4-bit dual scan display 4 level gray, 4-bit single scan display 4 level gray, 8-bit single scan display or 4-bit dual scan display 16 level gray, 4-bit single scan display 16 level gray, 8-bit single scan display or 4-bit dual scan display Color, 4-bit single scan display Color, 8-bit single scan display or 4-bit dual scan display MV Value 1/4 1/8 1/4 1/8 1/4 1/8 3/4 3/8
The LCDBASEU register value is the first address value of the frame buffer. The lowest 4 bits must be eliminated for burst 4 word access. The LCDBASEL register value is determined by LCD size and LCDBASEU. The LCDBASEL value is given by the following equation: LCDBASEL = LCDBASEU + LCDBASEL offset
15-34
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
Example 1: 160 x 160, 4-level gray, 80 frame/sec, 4-bit single scan display, HCLK frequency is 60 MHz WLH = 1, WDLY = 1. Data transmission rate = 160 x 160 x 80 x 1/4 = 512 kHz CLKVAL = 58, VCLK = 517KHz HOZVAL = 39, LINEVAL = 159 LINEBLANK =10 LCDBASEL = LCDBASEU + 3200
NOTE: The higher the system load is, the lower the cpu performance is.
Example 2 (Virtual screen register): 4 -level gray, Vertual screen size = 1024 x 1024, LCD size = 320 x 240, LCDBASEU = 0x64, 4-bit dual scan. 1 half-word = 8 pixels (4-level gray), Virtual screen 1 line = 128 half-word = 1024 pixels, LCD 1 line = 320 pixels = 40 half-word, OFFSIZE = 128 - 40 = 88 = 0x58, PAGEWIDTH = 40 = 0x28 LCDBASEL = LCDBASEU + (PAGEWIDTH + OFFSIZE) x (LINEVAL +1) = 100 + (40 +88) x 120 = 0x3C64
15-35
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
Gray Level Selection Guide S3C2400X01LCD controller can generate 16 gray level using FRC(frame rate control). The FRC characteristics may cause unexpected patterns in gray level. These unwanted erronous patterns may be shown in fast response LCD or at lower frame rates. Because the quality of LCD gray levels depends on LCD's own characteristics, the user has to select the good gray levels after viewing all gray levels on user's own LCD.
Please select the gray level quality through the following procedures. 1. Get the latest dithering pattern register value from SAMSUNG. 2. Display 16gray bar in LCD. 3. Change the frame rate into an optimal value. 4. Change the VM alternating period to get the best quality. 5. As viewing 16 gray bars, select the good gray levels, which is displayed well on your LCD. 6. Use only the good gray levels for quality.
LCD Refresh Bus Bandwidth Calculation Guide S3C2400X01LCD controller can supports various LCD display size. To select suitable LCD display size(for the flicker free LCD system application), the user have to consider the LCD refresh bus bandwidth determined by LCD display size, bit per pixel(bpp), frame rate, memory bus width, memory type and so on. LCD Data Rate(Byte/s) = bpp x (Horizontal display size) x (Vertical display size) x (Frame rate) /8 LCD DMA Burst Count(Times/s) = LCD Data Rate(Byte/s) /16(Byte) ; LCD DMA using 4words(16Byte) burst Pdma means LCD DMA access period. In other words, the value of Pdma is the period of four-beat burst(4-words burst) for video data fetch. So, Pdma is determined by memory type and memory setting. Eventually, LCD System Load is determined by LCD DMA Burst Count and Pdma. LCD System Load = LCD DMA Burst Count x Pdma
Example 3 : 640 x 480, 8bpp, 60 frame/sec, 16-bit data bus width, SDRAM(Trp=2HCLK / Trcd=2HCLK / CL=2HCLK) and HCLK frequency is 60 MHz LCD Data Rate = 8 x 640 x 480 x 60 / 8 = 18.432Mbyte/s LCD DMA Burst Count = 18.432 / 16 = 1.152M/s Pdma = (Trp+Trcd+CL+(2 x 4)+1) x (1/60MHz) = 0.250ms LCD System Load = 1.152 x 250 = 0.288 System Bus Occupation Rate = (0.288/1) x 100 = 28.8%
15-36
S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
Register Setting Guide (TFT LCD) The maximum VCLK frequency of the TFT LCD Controller is 15 MHz whenever HCLK frequency can use 60 MHz. For applications, the system timing must be considered to avoid under-run condition of the fifo of the lcd controller caused by memory bandwidth contention. The CLKVAL register value determines the frequency of VCLK and frame rate. Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } x {(HSPW+1) + (HBPD +1) + (HFPD+1) + (HOZVAL + 1) } x { 2 x ( CLKVAL+1 ) / ( SYSTEM CLK ) } ] Example 4 : TFT Resolution : 240 x 240, VSPW =2 , VBPD =14, LINEVAL = 239, VFPD =4 HSPW =25, HBPD =15, HOZVAL = 239, HFPD =1 CLKVAL = 5 HCLK = 60 M (hz) Below parameter must be referenced by LCD Size, and Driver specification: VSPW, VBPD, LINEVAL, VFPD, HSPW, HBPD, HOZVAL, HFPD If target frame rate is 60-70Hz then CLKVAL should be 5. So, Frame Rate = 67Hz
15-37
LCD CONTROLLER
S3C2400 RISC MICROPROCESSOR
NOTES
15-38
S3C2400 RISC MICROPROCESSOR
A/D CONVERTER
16
OVERVIEW
FEATURES -- Resolution: 10-bit
A/D CONVERTER
The 10-bit CMOS ADC (Analog to Digital Converter) of S3C2400 is a recycling type device with 8-channel analog inputs. It converts the analog input signal into 10-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.5MHz A/D converter clock. A/D converter operates with on-chip sample-and-hold function and power down mode is supported.
-- Differential Linearity Error: 1.0 LSB -- Integral Linearity Error: 2.0 LSB -- Maximum Conversion Rate: -- Low Power Consumption -- Power Supply Voltage: 3.3V -- Analog Input Range: 0 - 3.3V -- On-chip sample-and-hold function 500 KSPS
16-1
A/D CONVERTER
S3C2400 RISC MICROPROCESSOR
A/D CONVERTER OPERATION
BLOCK DIAGRAM Figure 16-1 shows the functional block diagram of S3C2400 A/D converter. Note that the A/D converter device is a recycling type.
AIN[7:0] MDAC MDAC
AVREF FLASH FLASH
PCLK
PSR
CONTROL LOGIC
EOC ADCDAT[11:0]
Figure 16-1. A/D Converter Functional Block Diagram
FUNCTION DESCRIPTIONS A/D Conversion Time When the PCLK frequency is 50MHz and the prescaler value is 49, total 10-bit conversion time is as follows. A/D converter freq. = 50MHz/(49+1) = 1MHz Conversion time = 1/(1MHz / 5cycles) = 1/200KHz = 5 us
NOTE: This A/D converter was designed to operate at maximum 2.5MHz clock, so the conversion rate can go up to 500 KSPS.
Standby Mode Standby mode is activated when ADCCON[2] is set to '1'. In this mode, A/D conversion operation is halted and ADCDAT register contains the previous converted data.
16-2
S3C2400 RISC MICROPROCESSOR
A/D CONVERTER
Programming Notes 1. The A/D converted data can be accessed by means of interrupt or polling method. With interrupt method the overall conversion time - from A/D converter start to converted data read - may be delayed because of the return time of interrupt service routine and data access time. With polling method, by checking the ADCCON[15] - end of conversion flag-bit, the read time from ADCDAT register can be determined. Another way for starting A/D conversion is provided. After ADCCON[1] - A/D conversion start-by-read mode-is set to 1, A/D conversion starts simultaneously whenever converted data is read.
2.
16-3
A/D CONVERTER
S3C2400 RISC MICROPROCESSOR
A/D CONVERTER SPECIAL REGISTERS
A/D CONVERTER CONTROL REGISTER (ADCCON) Register ADCCON Address 0x15800000 R/W R/W Description A/D Converter control Register Reset Value 0x3FC4
ADCCON ECFLG PRSCEN
Bit [15] [14] Reserved
Description
Initial State 0 0
A/D converter prescaler enable 0 = Disable 1 = Enable
PRSCVL
[13:6]
A/D converter prescaler value Data value: 1 - 255 Note that division factor is (N+1) when prescaler value is N. Analog input channel select 000 = AIN 0 001 = AIN 1 010 = AIN 2 011 = AIN 3 100 = AIN 4 101 = AIN 5 110 = AIN 6 111 = AIN 7 Standby mode select 0 = Normal operation mode 1 = Standby mode A/D conversion start by read 0 = Disable start by read operation 1 = Enable start by read operation A/D conversion starts by writing `1'. Write) 0 = No operation 1 = A/D conversion starts Read) 0 = A/D conversion is completed. 1 = A/D conversion is being processed.
0xFF
INPUT SELECT
[5:3]
0
STDBM
[2]
1
READ _ START ENABLE _START
[1]
0
[0]
0
16-4
S3C2400 RISC MICROPROCESSOR
A/D CONVERTER
A/D CONVERTER DATA REGISTER (ADCDAT) Register ADCDAT Address 0x15800004 R/W R Description A/D converter data register Reset Value -
ADCDAT ADCDAT
Bit [9:0]
Description A/D converter data value Data value: 0 - 3FF Note that the converted data is loaded automatically after ADCCON[15] goes to 1.
Initial State -
16-5
A/D CONVERTER
S3C2400 RISC MICROPROCESSOR
NOTES
16-6
S3C2400 RISC MICROPROCESSOR
REAL TIME CLOCK
17
OVERVIEW
FEATURE
RTC (REAL TIME CLOCK)
The RTC (Real Time Clock) unit can be operated by the backup battery while the system power is off. The RTC can transmit 8-bit data to CPU as BCD (Binary Coded Decimal) values using the STRB/LDRB ARM operation. The data include second, minute, hour, date, day, month, and year. The RTC unit works with an external 32.768 kHz crystal and also can perform the alarm function.
-- BCD number: second, minute, hour, date, day, month, year -- Leap year generator -- Alarm function: alarm interrupt or wake-up from power down mode. -- Year 2000 problem is removed. -- Independent power pin (RTCVDD) -- Supports millisecond tick time interrupt for RTOS kernel time tick. -- Round reset function
17-1
S3C2400 RISC MICROPROCESSOR
REAL TIME CLOCK
REAL TIME CLOCK OPERATION
TICNT Time Tick Generator 128 Hz 215 Clock Divider XTIrtc 1 Hz SEC XTOrtc MIN HOUR DATE DAY MON RTCRST Reset Register Leap Year Generator
TIME TICK
YEAR
Control Register RTCCON
Alarm Generator RTCALM
PMWKUP
PWDN
ALMINT
Figure 17-1. Real Time Clock Block Diagram LEAP YEAR GENERATOR This block can determine whether the last date of each month is 28, 29, 30, or 31, based on data from BCDDAY, BCDMON, and BCDYEAR. This block considers the leap year in deciding on the last date. An 8-bit counter can only represent 2 BCD digits, so it cannot decide whether 00 year is a leap year or not. For example, it can not discriminate between 1900 and 2000. To solve this problem, the RTC block in S3C2400X01 has hard-wired logic to support the leap year in 2000. Please note 1900 is not leap year while 2000 is leap year. Therefore, two digits of 00 in S3C2400X01 denote 2000, not 1900. READ/WRITE REGISTERS Bit 0 of the RTCCON register must be set to high in order to write the BCD register in RTC block. To display the sec., min., hour, date, month, and year, the CPU should read the data in BCDSEC, BCDMIN, BCDHOUR, BCDDAY, BCDDATE, BCDMON, and BCDYEAR registers, respectively, in the RTC block. However, a one second deviation may exist because multiple registers are read. For example, when the user reads the registers from BCDYEAR to BCDMIN, the result is assumed to be 2059(Year), 12(Month), 31(Date), 23(Hour) and 59(Minute). When the user read the BCDSEC register and the result is a value from 1 to 59(Second), there is no problem, but, if the result is 0 sec., the year, month, date, hour, and minute may be changed to 2060(Year), 1(Month), 1(Date), 0(Hour) and 0(Minute) because of the one second deviation that was mentioned. In this case, user should re-read from BCDYEAR to BCDSEC if BCDSEC is zero. BACKUP BATTERY OPERATION The RTC logic can be driven by the backup battery, which supplies the power through the RTCVDD pin into RTC block, even if the system power is off. When the system off, the interfaces of the CPU and RTC logic should be blocked, and the backup battery only drives the oscillation circuit and the BCD counters to minimize power dissipation.
17-2
S3C2400 RISC MICROPROCESSOR
REAL TIME CLOCK
ALARM FUNCTION The RTC generates an alarm signal at a specified time in the power down mode or normal operation mode. In normal operation mode, the alarm interrupt (ALMINT) is activated. In the power down mode the power management wakeup (PMWKUP) signal is activated as well as the ALMINT. The RTC alarm register, RTCALM, determines the alarm enable/disable and the condition of the alarm time setting. TICK TIME INTERRUPT The RTC tick time is used for interrupt request. The TICNT register has an interrupt enable bit and the count value for the interrupt. The count value reaches '0' when the tick time interrupt occurs. Then the period of interrupt is as follow: Period = ( n+1 ) / 128 second n: Tick time count value (1-127) This RTC time tick may be used for RTOS(real time operating system) kernel time tick. If time tick is generated by RTC time tick, the time related function of RTOS will always synchronized with real time. ROUND RESET FUNCTION The round reset function can be performed by the RTC round reset register, RTCRST. The round boundary (30, 40, or 50 sec) of the second carry generation can be selected, and the second value is rounded to zero in the round reset. For example, when the current time is 23:37:47 and the round boundary is selected to 40 sec, the round reset changes the current time to 23:38:00. NOTE All RTC registers have to be accessed by the byte unit using the STRB,LDRB instructions or char type pointer.
32.768 KHZ X-TAL CONNECTION EXAMPLE The Figure 17-2 is an example circuit of the RTC unit oscillation at 32.768 kHz.
15-22pF XTIrtc 32768 Hz XTOrtc
Figure 17-2. Main Oscillator Circuit Examples
17-3
S3C2400 RISC MICROPROCESSOR
REAL TIME CLOCK
REAL TIME CLOCK SPECIAL REGISTERS
REAL TIME CLOCK CONTROL REGISTER (RTCCON) The RTCCON register consists of 4 bits such as the RTCEN, which controls the read/write enable of the BCD registers, CLKSEL, CNTSEL, and CLKRST for testing. RTCEN bit can control all interfaces between the CPU and the RTC, so it should be set to 1 in an RTC control routine to enable data read/write after a system reset. Also before power off, the RTCEN bit should be cleared to 0 to prevent inadvertent writing into RTC registers. Register RTCCON Address 0x15700040(L) 0x15700043(B) R/W Description Reset Value 0x0
R/W RTC control Register (by byte)
RTCCON RTCEN
Bit [0] RTC control enable 0 = Disable
Description 1 = Enable
Initial State 0
NOTE: Only BCD time count and read operation can be performed.
CLKSEL
[1]
BCD clock select 0 = XTAL 1/215 divided clock 1 = Reserved (XTAL clock only for test) BCD count select 0 = Merge BCD counters 1 = Reserved (Separate BCD counters) RTC clock count reset 0 = No reset, 1 = Reset
0
CNTSEL
[2]
0
CLKRST
[3]
0
NOTES: 1. All RTC registers have to be accessed by byte unit using STRB and LDRB instructions or char type pointer. 2. (L): When the endian mode is little endian. (B): When the endian mode is Big endian.
TICK TIME COUNT REGISTER (TICNT) Register TICNT Address 0x15700044(L) 0x15700047(B) R/W R/W (by byte) Description Tick time count Register Reset Value 0x00000000
TICNT TICK INT ENABLE TICK TIME COUNT
Bit [7] [6:0]
Description Tick time interrupt enable 0 = disable 1 = enable Tick time count value. (1-127) This counter value decreases internally, and users can not read this real counter value in working.
Initial State 0 000000
17-4
S3C2400 RISC MICROPROCESSOR
REAL TIME CLOCK
RTC ALARM CONTROL REGISTER (RTCALM) RTCALM register determines the alarm enable and the alarm time. Note that the RTCALM register generates the alarm signal through both ALMINT and PMWKUP in power down mode, but only through ALMINT in the normal operation mode. Register RTCALM Address 0x15700050(L) 0x15700053(B) R/W Description Reset Value 0x00
R/W RTC alarm control Register (by byte)
RTCALM Reserved ALMEN YEAREN MONREN DAYEN HOUREN MINEN SECEN
Bit [7] [6] [5] [4] [3] [2] [1] [0] Reserved to 0. Alarm global enable 0 = Disable, Year alarm enable 0 = Disable, Month alarm enable 0 = Disable, Day alarm enable 0 = Disable, Hour alarm enable 0 = Disable,
Description
Initial State 0 0
1 = Enable 0 1 = Enable 0 1 = Enable 0 1 = Enable 0 1 = Enable 0 0
Minute alarm enable 0 = Disable, 1 = Enable Second alarm enable 0 = Disable, 1 = Enable
17-5
S3C2400 RISC MICROPROCESSOR
REAL TIME CLOCK
ALARM SECOND DATA REGISTER (ALMSEC) Register ALMSEC Address 0x15700054(L) 0x15700057(B) R/W R/W (by byte) Description Alarm second data Register Reset Value 0x00
ALMSEC Reserved SECDATA
Bit [7] [6:4] [3:0]
Description
Initial State 0
BCD value for alarm second from 0 to 5 from 0 to 9
000 0000
ALARM MIN DATA REGISTER (ALMMIN) Register ALMMIN Address 0x15700058(L) 0x1570005B(B) R/W R/W (by byte) Description Alarm minute data Register Reset Value 0x00
ALMMIN Reserved MINDATA
Bit [7] [6:4]
Description
Initial State 0
BCD value for alarm minute from 0 to 5 from 0 to 9
000 0000
[3:0]
ALARM HOUR DATA REGISTER (ALMHOUR) Register ALMHOUR Address 0x1570005C(L) 0x1570005F(B) R/W R/W (by byte) Description Alarm hour data Register Reset Value 0x00
ALMHOUR Reserved HOURDATA
Bit [7:6] [5:4]
Description
Initial State 0
BCD value for alarm hour from 0 to 2 from 0 to 9
00 0000
[3:0]
17-6
S3C2400 RISC MICROPROCESSOR
REAL TIME CLOCK
ALARM DAY DATA REGISTER (ALMDAY) Register ALMDAY Address 0x15700060(L) 0x15700063(B) R/W Description Reset Value 0x01
R/W Alarm day data Register (by byte)
ALMDAY Reserved DAYDATA
Bit [7:6] [5:4]
Description
Initial State 0
BCD value for alarm day, from 0 to 28, 29, 30, 31 from 0 to 3 from 0 to 9
00 0001
[3:0]
ALARM MON DATA REGISTER (ALMMON) Register ALMMON Address 0x15700064(L) 0x15700067(B) R/W R/W (by byte) Description Alarm month data Register Reset Value 0x01
ALMMON Reserved MONDATA
Bit [7:5] [4]
Description
Initial State 0
BCD value for alarm month from 0 to 1 from 0 to 9
0 0001
[3:0]
ALARM YEAR DATA REGISTER (ALMYEAR) Register ALMYEAR Address 0x15700068(L) 0x1570006B(B) R/W Description Reset Value 0x00
R/W Alarm year data Register (by byte)
ALMYEAR YEARDATA
Bit [7:0] BCD value for year from 00 to 99
Description
Initial State 0x00
17-7
S3C2400 RISC MICROPROCESSOR
REAL TIME CLOCK
RTC ROUND RESET REGISTER (RTCRST) Register RTCRST Address 0x1570006C(L) 0x1570006F(B) R/W Description Reset Value 0x0.
R/W RTC round reset Register (by byte)
RTCRST SRSTEN SECCR
Bit [3] [2:0]
Description Round second reset enable 0 = Disable, 1 = Enable Round boundary for second carry generation. 011 = over than 30 sec 100 = over than 40 sec 101 = over than 50 sec
NOTE: If other values(0,1,2,6,7) are set, no second carry is generated. But second value can be reset.
Initial State 0 00
BCD SECOND REGISTER (BCDSEC) Register BCDSEC Address 0x15700070(L) 0x15700073(B) R/W R/W (by byte) Description BCD second Register Reset Value Undef.
BCDSEC SECDATA
Bit [6:4] [3:0] BCD value for second from 0 to 5 from 0 to 9
Description
Initial State - -
BCD MINUTE REGISTER (BCDMIN) Register BCDMIN Address 0x15700074(L) 0x15700077(B) R/W R/W (by byte) Description BCD minute Register Reset Value Undef.
BCDMIN MINDATA
Bit [6:4] [3:0] BCD value for minute from 0 to 5 from 0 to 9
Description
Initial State - -
17-8
S3C2400 RISC MICROPROCESSOR
REAL TIME CLOCK
BCD HOUR REGISTER (BCDHOUR) Register BCDHOUR Address 0x15700078(L) 0x1570007B(B) R/W Description Reset Value Undef.
R/W BCD hour Register (by byte)
BCDHOUR Reserved HOURDATA
Bit [7:6] [5:4] [3:0] BCD value for hour from 0 to 2 from 0 to 9
Description
Initial State - - -
BCD DAY REGISTER (BCDDAY) Register BCDDAY Address 0x1570007C(L) 0x1570007F(B) R/W Description Reset Value Undef
R/W BCD day Register (by byte)
BCDDAY Reserved DAYDATA
Bit [7:6] [5:4] [3:0] BCD value for day from 0 to 3 from 0 to 9
Description
Initial State - - -
BCD DATE REGISTER (BCDDATE) Register BCDDATE Address 0x15700080(L) 0x15700083(B) R/W Description Reset Value Undef.
R/W BCD date Register (by byte)
BCDDATE Reserved DATEDATA
Bit [7:3] [2:0] BCD value for date from 1 to 7
Description
Initial State - -
17-9
S3C2400 RISC MICROPROCESSOR
REAL TIME CLOCK
BCD MONTH REGISTER (BCDMON) Register BCDMON Address 0x15700084(L) 0x15700087(B) R/W Description Reset Value Undef.
R/W BCD month Register (by byte)
BCDMON Reserved MONDATA
Bit [7:5] [4] [3:0] BCD value for month from 0 to 1 from 0 to 9
Description
Initial State - - -
BCD YEAR REGISTER (BCDYEAR) Register BCDYEAR Address 0x15700088(L) 0x1570008B(B) R/W Description Reset Value Undef.
R/W BCD year Register (by byte)
BCDYEAR YEARDATA
Bit [7:0] BCD value for year from 00 to 99
Description
Initial State -
17-10
S3C2400 RISC MICROPROCESSOR
WATCHDOG TIMER
18
OVERVIEW
FEATURES
WATCHDOG TIMER
The S3C2400 watchdog timer is used to resume the controller operation when it had been disturbed by malfunctions such as noise and system errors. It can be used as a normal 16-bit interval timer to request interrupt service. The watchdog timer generates the reset signal for 128 PCLK cycles.
-- Normal interval timer mode with interrupt request -- Internal reset signal is activated for 128 PCLK cycles when the timer count value reaches 0 (time-out).
18-1
WATCHDOG TIMER
S3C2400 RISC MICROPROCESSOR
WATCH-DOG TIMER OPERATION The functional block diagram of the watchdog timer is shown in Figure 18-1. The watchdog timer uses PCLK as its only source clock. To generate the corresponding watchdog timer clock, the PCLK frequency is prescaled first, and the resulting frequency is divided again.
MUX 1/16 1/32 PCLK 8-bit Prescaler 1/64 1/128
WTDAT Interrupt WTCNT (Down Counter)
Reset Signal Generator
RESET
WTCON[15:8]
WTCON[4:3]
WTCON[2]
WTCON[0]
Figure 18-1. Watch-Dog Timer Block Diagram The prescaler value and the frequency division factor are specified in the watchdog timer control register, WTCON. The valid prescaler values range from 0 to 28-1. The frequency division factor can be selected as 16, 32, 64, or 128. Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle: t_watchdog = 1/( PCLK / (Prescaler value + 1) / Division_factor ) WTDAT & WTCNT When the watchdog timer is enabled first, the value of WTDAT (watchdog timer data register) cannot be automatically reloaded into the WTCNT (timer counter). For this reason, an initial value must be written to the watchdog timer count register, WTCNT, before the watchdog timer starts. CONSIDERATION OF DEBUGGING ENVIRONMENT When S3C2400 is in debug mode using Embedded ICE, the watch-dog timer must not operate. The watch-dog timer can determine whether or not the current mode is the debug mode from the CPU core signal (DBGACK signal). Once the DBGACK signal is asserted, the reset output of the watch-dog timer is not activated when the watchdog timer is expired.
18-2
S3C2400 RISC MICROPROCESSOR
WATCHDOG TIMER
WATCH-DOG TIMER SPECIAL REGISTERS
WATCH-DOG TIMER CONTROL REGISTER (WTCON) Using the Watch-Dog Timer Control register, WTCON, you can enable/disable the watch-dog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watch-dog timer output. The Watch-dog timer is used to resume the S3C2400X01 restart on mal-function after power-on; if controller restart is not desired, the Watch-dog timer should be disabled. If the user wants to use the normal timer provided by the Watch-dog timer, please enable the interrupt and disable the Watch-dog timer. Register WTCON Address 0x15300000 R/W R/W Description Watch-dog timer control Register Reset Value 0x8021
WTCON Prescaler value Reserved Watch-dog timer enable/disable Clock select
Bit [15:8] [7:6] [5]
Description the prescaler value The valid range is from 0 to (28-1) Reserved. These two bits must be 00 in normal operation. Enable or disable bit of Watch-dog timer. 0 = Disable Watch-dog timer 1 = Enable Watch-dog timer This two bits determines the clock division factor. 00: 16 01: 32 10: 64 11: 128 Enable or disable bit of the interrupt. 0 = Disable interrupt generation 1 = Enable interrupt generation Reserved. This bit must be 0 in normal operation Enable or disable bit of Watch-dog timer output for reset signal: 1: Asserts reset signal of the S3C2400X01 at watch-dog time-out 0: Disables the reset function of the watch-dog timer.
Initial State 0x80 00 1
[4:3]
00
Interrupt enable/disable Reserved Reset enable/disable
[2]
0
[1] [0]
0 1
18-3
WATCHDOG TIMER
S3C2400 RISC MICROPROCESSOR
WATCH-DOG TIMER DATA REGISTER (WTDAT) The watchdog timer data register, WTDAT is used to specify the time-out duration. The content of WTDAT can not be automatically loaded into the timer counter at initial watchdog timer operation. However, the first time-out occurs by using 0x8000(initial value), after then the value of WTDAT will be automatically reloaded into WTCNT. Register WTDAT Address 0x15300004 R/W R/W Description Watch-dog timer data Register Reset Value 0x8000
WTDAT Count reload value
Bit [15:0]
Description Watch-dog timer count value for reload.
Initial State 0x8000
WATCH-DOG TIMER COUNT REGISTER (WTCNT) The watchdog timer count register, WTCNT, contains the current count values for the watchdog timer during normal operation. Note that the content of the watchdog timer data register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially, so the watchdog timer count register must be set to an initial value before enabling it. Register WTCNT Address 0x15300008 R/W R/W Description Watch-dog timer count Register Reset Value 0x8000
WTCNT Count value
Bit [15:0]
Description The current count value of the watch-dog timer
Initial State 0x8000
18-4
S3C2400 RISC MICROPROCESSOR
MMC INTERFACE
19
OVERVIEW
FEATURES
MMC INTERFACE
The S3C2400 MultiMediaCard (MMC) interface can interface with MMC type (referenced MMCA ver 2.11) serial data. There are four tokens in the MMC type serial data; transmit command, receive response, transmit data, receive data. MMC module needs to transfer these four tokens respectively. We will design MMC interface with four part division as Block Diagram. If MMC module transmits or receives data, each FIFO should always operate. However, if MMC module transmits command or receives response, neither FIFO nor DMA mode are not supplied.
-- MultiMediaCard protocol (ver 2.11) compatible -- 16 bytes FIFO (depth 16) for the data transmission -- 16 bytes FIFO (depth 16) for the data receiving. -- 40-bit Command Register -- 128-bit Response Register -- 8-bit Prescaler logic (Freq. = System Clock / (2(P + 1))) -- CRC7 & CRC16 generator -- Data Fault Error detection logic -- Normal, Interrupt, and DMA transfer mode
19-1
S3C2400 RISC MICROPROCESSOR
MMC INTERFACE
BLOCK DIAGRAM
Prescaler Register
PCLK
8bit Prescaler
Clock Logic
MMCLK
32
MMCMD (5byte)
8
Command Transmitter
TX_CMD
32 Data Bus
MMRSP (16byte)
8
Response Receiver
RX_CMD
CRC7 8 TxFIFO (16byte) 8 Data Transmitter TX_DAT
8
RxFIFO (16byte)
8 Data Receiver RX_DAT
CRC16
Figure 19-1. MMC Block Diagram
19-2
S3C2400 RISC MICROPROCESSOR
MMC INTERFACE
MMC OPERATION
A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. The transmission frequency is controlled by making the appropriate bit settings to the MMPRE register. You can modify its frequency to adjust the baud rate data register value. PROGRAMMING PROCEDURE To program the MMC modules, follow these basic steps : 1. 2. 3. 4. 5. 6. 7. 8. 9. Set Baud Rate Prescaler Register(MMPRE). Set MMCON, and MMFCON to configure properly the MMC module and FIFO, and Block Length Register(MMLEN). Wait 74 MMCLK clock cycle in order to initialize the card. Write command 5byte to MMCMD Start command transmit and determine command types with setting MMCRR register. Tx data Write data to Data Register(MMDAT) while Tx FIFO is not beyond trigger level. Rx data Data receiver starts operation when MMC module detects start bit in DAT pin. User can read data from Rx FIFO when Rx FIFO reaches trigger level or Rx FIFO has the last data of a block. Confirm the end of MMC command operation when NCFIN(Normal Command Finish) flag, or DCFIN(Data Command Finish) flag of MMSTA register is set Clear the corresponding flag(NCFIN, or DCFIN) of MMSTA through writing one with this bit.
STEPS FOR TRANSMIT BY DMA 1. 2. 3. 4. 5. DMA is configured properly and the MMC is configured as DMA start with MMC Mode Select bits. If Tx FIFO is beyond trigger level, go to step 4. The MMC requests DMA service, and then DMA transmits 1byte data to MMC module until FIFO is full. The MMC transmits the data to card. Go to step 2 until DMA count is 0.
STEPS FOR RECEIVE BY DMA 1. 2. 3. 4. 5. DMA is configured properly and the MMC is configured as DMA start with MMC Mode Select bits. The MMC receives the data from card. If Rx FIFO neither reaches trigger level nor has the last data of a block, go to step 2. The MMC requests DMA service, and then DMA receives 1byte data from MMC module until FIFO is empty. Go to step 2 until DMA count is 0.
19-3
S3C2400 RISC MICROPROCESSOR
MMC INTERFACE
MMC SPECIAL REGISTERS
MMC CONTROL REGISTER (MMCON) Register MMCON Address 0x15A00000(Li/B, Li/HW, Li/W, Bi/W) 0x15A00002(Bi/HW) 0x15A00003(Bi/B) Bit [7:6] [5] Determines MMC generate an interrupt if an exception(CRC error etc) or transfer completion occur. 0 = disable, [4:3] 1 = interrupt enable 00 0 R/W R/W Description MMC Control Register Reset Value 0x00
MMCON Reserved Exception Interrupt Enable (EINTE) MMC Mode Select (MMOD)
Description
Initial State
Determines how the MMC interface is read/written. 00 = polling mode, 01 = interrupt mode 10 = DMA transmit mode, 11 = DMA receive mode
Prescaler Enable (ENPRE) Clock Polarity Select (CPOL) Clock Pending mode(PEND)
[2] [1] [0]
Determines what you want prescaler enable or not. 0 = counter reset, 1 = enable prescaler Determines an active high or active low clock. 0 = active high, 1 = active low Determines clock pends when APB is not ready to transfer data. 0 = disable, 1 = clock pending mode enable
0 0 0
NOTES: 1. When Clock Pending mode state is disable, if receive data collision error occurs and invalid data transmit error occurs, MMSTA[2], MMSTA[3] is set. 2. (Li/B/HW/W): Access by byte/half-word/word unit when the endian mode is Little. (Bi/B/HW/W): Access by byte/half-word/word unit when the endian mode is Big.
19-4
S3C2400 RISC MICROPROCESSOR
MMC INTERFACE
MMC COMMAND RELATED REGISTER (MMCRR) Register MMCRR Address 0x15A00004(Li/B, Li/HW, Li/W, Bi/W) 0x15A00006(Bi/HW) 0x15A00007(Bi/B) Bit [7:6] R/W R/W Description MMC Command Related Register Reset Value 0x00
MMCRR Response Type (RTYP) Multi Block Mode (MULTI) Sequential Mode (SEQ) Data Stop Command (STOP) Data Read Command (RCMD) Data Write Command (WCMD) Command Start (CMST)
NOTE:
Description Determines what response type MMC command is. 00 = no response, 01 = short type (5 byte) 10 = short & busy type (5 byte), 11 = long type (16 byte) Determines whether MMC command type is MULTI or not. 0 = normal mode, 1 = multi mode Determines whether MMC command type is SEQ or not. 0 = normal mode, 1 = sequential mode Determines whether MMC command function is STOP or not. 0 = not stop command, 1 = stop command Determines whether MMC command function is READ or not. 0 = not read command, 1 = read command Determines whether MMC command function is WRITE or not. 0 = not write command, 1 = write command Determines whether MMC command operation starts or not. 0 = command ready, 1 = command start
Initial State 00
[5] [4] [3]
0 0 0
[2]
0
[1]
0
[0]
0
When you are going to operate STOP command, confirm transmit(or receive) all the data to send (or get). And then, you can execute STOP command. But, in the case of sequential(SEQ) write(WCMD) command, you should but also watch Tx FIFO's count number whether zero or not.
19-5
S3C2400 RISC MICROPROCESSOR
MMC INTERFACE
MMCRR REGISTER SETTING ACCORDING TO MULTI MEDIA CARD CMD CMD No. CMD0 CMD2 CMD4 CMD7 CMD7 CMD9 CMD10 CMD11 CMD12 CMD15 CMD17 CMD18 CMD20 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30 CMD38 other
NOTE:
Operation Go Idle All Send CID Set DSR Card select Card deselect Send CSD Send CID Read Seq Data Stop Transfer Go Inactive State Read Single Block Read Multi Block Write Seq Data Write Single Block Write Multi Block Program CID Program CSD Set Write Protect Clr Write Protect Send Write Protect Erase The Other CMD
RTYP 0 3 0 1 0 3 3 1 1 0 1 1 1 1 1 1 1 2 2 1 2 1
MULTI 0 0 0 0 0 0 0 0 0 0 0 set 0 0 set 0 0 0 0 0 0 0
SEQ 0 0 0 0 0 0 0 set 0 0 0 0 set 0 0 0 0 0 0 0 0 0
STOP 0 0 0 0 0 0 0 0 set 0 0 0 0 0 0 0 0 0 0 0 0 0
RCMD 0 0 0 0 0 0 0 set 0 0 set set 0 0 0 0 0 0 0 set 0 0
WCMD 0 0 0 0 0 0 0 0 0 0 0 0 set set set set Set 0 0 0 0 0
Finish Flag Normal Normal Normal Normal Normal Normal Normal Data Normal Normal Data Data Data Data Data Data Data Normal Normal Data Normal Normal
If you transmit CMD2 several times moer than the number of cards attatched, you must add to transmit dummy data through CMD bus. You can know the number of cards attatched when NCFIN flag wll not set although 189 MMCCLK cycles running(during the minimum length loop of 160 times) after starting CMD2. Typical value of dummy data are 0x00, 0x00, 0x00, 0x00, 0x00(5bytes). You put these value in the MMCMD0, MMCMD1 register, and then set MMCRR register to 0x01.
19-6
S3C2400 RISC MICROPROCESSOR
MMC INTERFACE
MMC FIFO CONTROL REGISTER (MMFCON) Register MMFCON Address 0x15A00008(Li/B, Li/HW, Li/W, Bi/W) 0x15A0000A(Bi/HW) 0x15A0000B(Bi/B) Bit [7:6] [5:4] Determines trigger level of transmit FIFO 00 = empty, 01 = 4 byte 10 = 8 byte 11 = 12 byte Determines trigger level of receive FIFO. 00 = 4 byte, 01 = 8 byte 10 = 12 byte 11 = 16 byte Determines resetting for transmit FIFO. 0 = normal mode, 1 = Tx FIFO reset Determines resetting for receive FIFO. 0 = normal mode, 1 = Rx FIFO reset 00 R/W R/W Description MMC FIFO Control Register Reset Value 0x00
MMFCON Reserved Tx FIFO Trigger level (TFTRIG) Rx FIFO Trigger level (RFTRIG) Tx FIFO Reset (TFRST) Rx FIFO Reset (RFRST)
NOTE:
Description
Initial State
[3:2]
00
[1] [0]
0 0
You must always reset Tx FIFO or Rx FIFO, after completion MULTI command operation and SEQ command operation. FIFO may have some of dummy data in these commands.
19-7
S3C2400 RISC MICROPROCESSOR
MMC INTERFACE
MMC STATUS REGISTER (MMSTA) Register MMSTA Address 0x15A0000C(Li/B, Li/HW, Li/W, Bi/W) 0x15A0000E(Bi/HW) 0x15A0000F(Bi/B) Bit [7] [6] This flag is set when response token value is wrong. This flag is cleared by reading the MMSTA with RCRC set. 0 = not occur, 1 = CRC error occur This flag is set when data reading token value is wrong. This flag is cleared by reading the MMSTA with DCRC set. 0 = not occur, 1 = CRC error occur This flag is set when data writing token is wrong. This flag is cleared by reading the MMSTA with CRCS set. 0 = not occur, 1 = CRC status error occur This flag is set when invalid data should be transmitted because there is no data in the transmit FIFO. This flag is cleared by reading the MMSTA with INVL set. 0 = not detect, 1 = invalid data Tx error detect This flag is set when data collision occurs in the receive FIFO. This flag is cleared by reading the MMSTA with RCOL set. 0 = not detect, 1 = collision error detect This bit indicates that data transfer related command operation completes. This flag is cleared by setting to one this bit. 0 = not finish, 1 = data command finish This bit indicates that normal command operation completes. This flag is cleared by setting to one this bit. 0 = not finish, 1 = normal command finish 0 0 R/W R/(C) Description MMC Status Register Reset Value 0x00
MMSTA Reserved Response CRC Mismatch Error (RCRC) Data Read CRC Mismatch Error (DCRC) CRC Status Error (CRCS) Invalid Data Transmit Error (INVL) Receive Data Collision Error (RCOL) Data Command Finish (DCFIN) Normal Command Finish (NCFIN)
Description
Initial State
[5]
0
[4]
0
[3]
0
[2]
0
[1] R/C [0] R/C
NOTES: 1. DCFIN bit is set after the data transfer 2. In case of the command with the response , NCFIN bit is set after the response. In case of the command without the response, NCFIN bit is set after the command transfer.
19-8
S3C2400 RISC MICROPROCESSOR
MMC INTERFACE
MMC FIFO STATUS REGISTER (MMFSTA) Register MMFSTA Address 0x15A00010(Li/HW, Li/W, Bi/W) 0x15A00012(Bi/HW) Bit [15:12] [11:8] [7:4] [3] [2] [1] Number of data in transmit FIFO Number of data in receive FIFO This bit automatically set to 1 whenever transmit FIFO is full. 0 = 0 Tx FIFO 15, 1 = Full This bit automatically set to 1 whenever receive FIFO is full. 0 = 0 Rx FIFO 15, 1 = Full This bit indicates that Tx FIFO reaches MMFCON's trigger level. 0 = not detect, 1 = detect This bit indicates that Rx FIFO reaches MMFCON's trigger level or Rx FIFO has the last data of a block. 0 = not detect, 1 = detect 0000 0000 0 0 0 R/W R Description MMC FIFO Status Register Reset Value 0x0000
MMFSTA Reserved Tx FIFO Count (TFCNT) Rx FIFO Count (RFCNT) Tx FIFO Full (TFFULL) Rx FIFO Full (RFFULL) Tx FIFO Trigger level Detect (TFDET) Rx FIFO Trigger level Detect (RFDET)
Description
Initial State
[0]
0
MMC BAUD RATE PRESCALER REGISTER (MMPRE) Register MMPRE Address 0x15A00014 (Li/B, Li/HW, Li/W, Bi/W) 0x15A00016 (Bi/HW) 0x15A00017 (Bi/B) Bit [7:0] R/W R/W Description MMC Baud Rate Prescaler Register Reset Value 0x00
MMPRE Prescaler Value
Description Determines MMC clock rate as below equation. Baud rate = PCLK / 2 / (Prescaler value + 1)
Initial State 0x00
MMC BLOCK LENGTH REGISTER (MMLEN) Register MMLEN Address 0x15A00018(Li/HW, Li/W, Bi/W) 0x15A0001A(Bi/HW) Bit [15:0] R/W R/W Description MMC Block Length Register Reset Value 0x0000
MMLEN Block Length Value
Description Determines the block size to transfer data
Initial State 0x0000
19-9
S3C2400 RISC MICROPROCESSOR
MMC INTERFACE
19-10
S3C2400 RISC MICROPROCESSOR
MMC INTERFACE
RESPONSE CRC7 REGISTER (MMCR7) Register MMCR7 Address 0x15A0001C(Li/B, Li/HW, Li/W, Bi/W) 0x15A0001E(Bi/HW) 0x15A0001F(Bi/B) Bit [7:1] [0] R/W R Description Response CRC7 Register Reset Value 0x00
RCRC7 Response CRC7 value Response Endbit
Description This field contains the Response CRC7 value. This field contains the Response Endbit.
Initial State 0x00 0x0
MMC RESPONSE STATUS REGISTER 0 (MMRSP0) Register MMRSP0 MMRSP Response Register Response Register Response Register Response Register Address 0x15A00020 Bit [31:24] [23:16] [15:8] [7:0] Little 4 byte 3rd byte 2nd byte 1st byte
th
R/W R
Description MMC Response Status Register 0 Big Description This field contains the response value to be received over the MMC channel. This field contains the response value to be received over the MMC channel. This field contains the response value to be received over the MMC channel. This field contains the response value to be received over the MMC channel.
Reset Value 0x00000000 Initial State 0x00 0x00 0x00 0x00
1 byte 2nd byte 3rd byte 4th byte
st
MMC RESPONSE STATUS REGISTER 1 (MMRSP1) Register MMRSP1 MMRSP Response Register Response Register Response Register Response Register Address 0x15A00024 Bit [31:24] [23:16] [15:8] [7:0] Little 8th byte 7th byte 6th byte 5th byte R/W R Big 5th byte 6th byte 7th byte 8th byte Description MMC Response Status Register 1 Description This field contains the response value to be received over the MMC channel. This field contains the response value to be received over the MMC channel. This field contains the response value to be received over the MMC channel. This field contains the response value to be received over the MMC channel. Reset Value 0x00000000 Initial State 0x00 0x00 0x00 0x00
19-11
S3C2400 RISC MICROPROCESSOR
MMC INTERFACE
MMC RESPONSE STATUS REGISTER 2 (MMRSP2) Register MMRSP2 MMRSP Response Register Response Register Response Register Response Register Address 0x15A00028 Bit [31:24] [23:16] [15:8] [7:0] Little 12th byte 11th byte 10th byte 9th byte R/W R Big 9th byte Description MMC Response Status Register 2 Description This field contains the response value to be received over the MMC channel. Reset Value 0x00000000 Initial State 0x00 0x00 0x00 0x00
10th byte This field contains the response value to be received over the MMC channel. 11th byte This field contains the response value to be received over the MMC channel. 12th byte This field contains the response value to be received over the MMC channel.
MMC RESPONSE STATUS REGISTER 3 (MMRSP3) Register MMRSP3 MMRSP Response Register Response Register Response Register Response Register Address 0x15A0002C Bit [31:24] [23:16] [15:8] [7:0] Little 16 byte 15th byte 14th byte 13th byte
th
R/W R Big
th
Description MMC Response Status Register 3 Description
Reset Value 0x00000000 Initial State 0x00 0x00 0x00 0x00
13 byte This field contains the response value to be received over the MMC channel. 14th byte This field contains the response value to be received over the MMC channel. 15th byte This field contains the response value to be received over the MMC channel. 16th byte This field contains the response value to be received over the MMC channel.
MMC COMMAND REGISTER 0 (MMCMD0) Register MMCMD0 Address 0x15A00030(Li/B, Li/HW, Li/W, Bi/W) 0x15A00032(Bi/HW) 0x15A00033(Bi/B) Bit [7:0] R/W R/W Description MMC Command Register 0 Reset Value 0x00
MMCMD Command Register (1st byte)
Description This field contains the command value to be transmitted over the MMC channel.
Initial State 0x00
19-12
S3C2400 RISC MICROPROCESSOR
MMC INTERFACE
MMC COMMAND REGISTER 1 (MMCMD1) Register MMCMD1 MMCMD Command Register (2nd byte) Command Register (3rd byte) Command Register (4th byte) Command Register (5th byte) Address 0x15A00034 Bit [31:24] Little 4th byte R/W R/W Big 1st byte Description MMC Command Register 1 Description This field contains the command value to be transmitted over the MMC channel. This field contains the command value to be transmitted over the MMC channel. This field contains the command value to be transmitted over the MMC channel. This field contains the command value to be transmitted over the MMC channel. Reset Value 0x00000000 Initial State 0x00
[23:16]
3rd byte
2nd byte
0x00
[15:8]
2nd byte
3rd byte
0x00
[7:0]
1st byte
4th byte
0x00
DATA RECEIVE CRC16 BUFFER REGISTER (MMCR16) Register MMCR16 Address 0x15A00038(Li/HW, Li/W, Bi/W) 0x15A0003A(Bi/HW) Bit [15:0] R/W R Description Data Read CRC16 Buffer Register Reset Value 0x0000
CRC16B Data Read CRC16 value
Description This field contains the data receive CRC16 buffer value.
Initial State 0x0000
MMC DATA REGISTER (MMDAT) Register MMDAT Address 0x15A0003C(Li/B, Li/HW, Li/W, Bi/W) 0x15A0003E(Bi/HW) 0x15A0003F(Bi/B) Bit [7:0] R/W R/W Description MMC Data Register Reset Value 0x00
MMDAT Data Register
Description This field contains the data to be transmitted or received over the MMC channel
Initial State 0x00
19-13
S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
20
OVERVIEW
IIC-BUS INTERFACE
The S3C2400 RISC microprocessor can support a multi-master IIC-bus serial interface. A dedicated serial data line (SDA) and a serial clock line (SCL) carry information between bus masters and peripheral devices which are connected to the IIC-bus. The SDA and SCL lines are bi-directional. In multi-master IIC-bus mode, multiple S3C2400 RISC microprocessors can receive or transmit serial data to or from slave devices. The master S3C2400, which can initiate a data transfer over the IIC-bus, is responsible for terminating the transfer. Standard bus arbitration procedure is used in this IIC-bus in S3C2400. To control multi-master IIC-bus operations, values must be written to the following registers: -- Multi-master IIC-bus control register, IICCON -- Multi-master IIC-bus control/status register, IICSTAT -- Multi-master IIC-bus Tx/Rx data shift register, IICDS -- Multi-master IIC-bus address register, IICADD When the IIC-bus is free, the SDA and SCL lines should be both at High level. A High-to-Low transition of SDA can initiate a Start condition. A Low-to-High transition of SDA can initiate a Stop condition while SCL remains steady at High Level. The Start and Stop conditions can always be generated by the master devices. A 7-bit address value in the first data byte, which is put onto the bus after the Start condition has been initiated, can determine the slave device which the bus master device has selected. The 8th bit determines the direction of the transfer (read or write). Every data byte put onto the SDA line should total eight bits. The number of bytes which can be sent or received during the bus transfer operation is unlimited. Data is always sent from most-significant bit (MSB) first, and every byte should be immediately followed by an acknowledge (ACK) bit.
20-1
S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
Address Register
Comparator IIC-Bus Control Logic SCL PCLK IICCON IICSTAT 4-bit Prescaler Shift Register SDA
Shift Register (IICDS)
Data Bus
Figure 20-1. IIC-Bus Block Diagram
20-2
S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
THE IIC-BUS INTERFACE The S3C2400X01 IIC-bus interface has four operation modes: -- Master transmitter mode -- Master receive mode -- Slave transmitter mode -- Slave receive mode Functional relationships among these operating modes are described below. START AND STOP CONDITIONS When the IIC-bus interface is inactive, it is usually in slave mode. In other words, the interface should be in slave mode before detecting a Start condition on the SDA line.(A Start condition can be initiated with a High-to-Low transition of the SDA line while the clock signal of SCL is High) When the interface state is changed to the master mode, a data transfer on the SDA line can be initiated and SCL signal generated. A Start condition can transfer a one-byte serial data over the SDA line, and a stop condition can terminate the data transfer. A stop condition is a Low-to-High transition of the SDA line while SCL is High. Start and Stop conditions are always generated by the master. The IIC-bus is busy when a Start condition is generated. A few clocks after a Stop condition, the IIC-bus will be free, again. When a master initiates a Start condition, it should send a slave address to notify the slave device. The one byte of address field consist of a 7-bit address and a 1-bit transfer direction indicator (that is, write or read). If bit 8 is 0, it indicates a write operation(transmit operation); if bit 8 is 1, it indicates a request for data read(receive operation). The master will finish the transfer operation by transmitting a Stop condition. If the master wants to continue the data transmission to the bus, it should generate another Start condition as well as a slave address. In this way, the readwrite operation can be performed in various formats.
SDA
SDA
SCL
SCL
Start Condition
Stop Condition
Figure 20-2. Start and Stop Condition
20-3
S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. The number of bytes which can be transmitted per transfer is unlimited. The first byte following a Start condition should have the address field. The address field can be transmitted by the master when the IIC-bus is operating in master mode. Each byte should be followed by an acknowledgement (ACK) bit. The MSB bit of the serial data and addresses are always sent first.
Write Mode Format with 7-bit Addresses S Slave Address 7bits R/W A "0" (Write) DATA(1Byte) AP
Data Transferred (Data + Acknowledge)
Write Mode Format with 10-bit Addresses S Slave Address 1st 7 bits 11110XX R/W A "0" (Write) Slave Address 2nd Byte A DATA AP
Data Transferred (Data + Acknowledge)
Read Mode Format with 7-bit Addresses S Slave Address 7 bits R/W A "1" (Read) DATA AP
Data Transferred (Data + Acknowledge)
NOTES: 1. S: Start, rS: Repeat Start, P: Stop, A: Acknowledge 2. : From Master to Slave, : from Slave to Master
Figure 20-3. IIC-Bus Interface Data Format
20-4
S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
MSB
Acknowledgement Signal from Receiver
Acknowledgement Signal from Receiver
1 S
2
7
8
9 ACK
1
2
9
Byte Complete, Interrupt within Receiver
Clock Line Held Low until the interrupt pending flahg (IICCON[4]) is cleared.
Figure 20-4. Data Transfer on the IIC-Bus ACK SIGNAL TRANSMISSION To finish a one-byte transfer operation completely, the receiver should send an ACK bit to the transmitter. The ACK pulse should occur at the ninth clock of the SCL line. Eight clocks are required for the one-byte data transfer. The master should generate the clock pulse required to transmit the ACK bit. The transmitter should release the SDA line by making the SDA line High when the ACK clock pulse is received. The receiver should also drive the SDA line Low during the ACK clock pulse so that the SDA is Low during the High period of the ninth SCL pulse. The ACK bit transmit function can be enabled or disabled by software (IICSTAT). However, the ACK pulse on the ninth clock of SCL is required to complete a one-byte data transfer operation.
Clock to Output
Data Output by Transmitter
Data Output by Receiver
SCL from Master
S Start Condition
1
2
7
8
9
Clock Pulse for Acknowledgment
Figure 20-5. Acknowledge on the IIC-Bus
20-5
S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
READ-WRITE OPERATION In the transmitter mode, after the data is transferred, the IIC-bus interface will wait until IICDS(IIC-bus Data Shift Register) is written by a new data. Until the new data is written, the SCL line will be held low. After the new data is written to IICDS register, the SCL line will be released. The S3C2400X01 should hold the interrupt to identify the completion of current data transfer. After the CPU receives the interrupt request, it should write a new data into IICDS, again. In the receive mode, after a data is received, the IIC-bus interface will wait until IICDS register is read. Until the new data is read out, the SCL line will be held low. After the new data is read out from IICDS register, the SCL line will be released. The S3C2400X01 should hold the interrupt to identify the completion of the new data reception. After the CPU receives the interrupt request, it should read the data from IICDS. BUS ARBITRATION PROCEDURES Arbitration takes place on the SDA line to prevent the contention on the bus between two masters. If a master with a SDA High level detects another master with a SDA active Low level, it will not initiate a data transfer because the current level on the bus does not correspond to its own. The arbitration procedure will be extended until the SDA line turns High. However when the masters simultaneously lower the SDA line, each master should evaluate whether or not the mastership is allocated to itself. For the purpose of evaluation, each master should detect the address bits. While each master generates the slaver address, it should also detect the address bit on the SDA line because the lowering of SDA line is stronger than maintaining High on the line. For example, one master generates a Low as first address bit, while the other master is maintaining High. In this case, both masters will detect Low on the bus because Low is stronger than High even if first master is trying to maintain High on the line. When this happens, Low(as the first bit of address) -generating master will get the mastership and High(as the first bit of address) generating master should withdraw the mastership. If both masters generate Low as the first bit of address, there should be an arbitration for second address bit, again. This arbitration will continue to the end of last address bit. ABORT CONDITIONS If a slave receiver can not acknowledge the confirmation of the slave address, it should hold the level of the SDA line High. In this case, the master should generate a Stop condition and to abort the transfer. If a master receiver is involved in the aborted transfer, it should signal the end of the slave transmit operation by canceling the generation of an ACK after the last data byte received from the slave. The slave transmitter should then release the SDA to allow a master to generate a Stop condition. CONFIGURING THE IIC-BUS To control the frequency of the serial clock (SCL), the 4-bit prescaler value can be programmed in the IICCON register. The IIC-bus interface address is stored in the IIC-bus address register, IICADD. (By default, the IIC-bus interface address is an unknown value.)
20-6
S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
FLOWCHARTS OF THE OPERATIONS IN EACH MODE The following steps must be executed before any IIC tx/rx operations. 1) Write own slave address on IICADD register if needed. 2) Set IICCON Register. a) Enable interrupt b) Define SCL period 3) Set IICSTAT to enable Serial Output.
START Master Tx mode has been configured.
Write slave address to IICDS
Write 0xF0(M/T Start) to IICSTAT
The data of the IICDS is transmitted
ACK period and then interrupt is pending
Stop? N
Y
Write new data trasnmitted to IICDS
Write 0xD0(M/T Stop) to IICSTAT
Clear pending bit to resume
Clear Pending bit
The data of the IICDS is shifted to SDA
Wait until the stop condition takes effect. END
Figure 20-6. Operations for Master/Transmitter Mode
20-7
S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
START Master Rx mode has been configured.
Write slave address to IICDS
Write 0xB0(M/R Start) to IICSTAT
The data of the IICDS(slave address) is transmitted
ACK period and then interrupt is pending
Stop? N
Y
Read a new data from IICDS
Write 0x90(M/R Stop) to IICSTAT
Clear pending bit to resume
Clear Pending bit
SDA is shifted to IICDS
Wait until the stop condition takes effect. END
Figure 20-7. Operations for Master/Receiver Mode
20-8
S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
START Slave Tx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS(the received slave address) N
Matched? Y
The IIC address match interrupt is generated
Write data to IICDS
Clear pending bit to resume. Y
Stop? N
The data of the IICDS is shifted to SDA
END
Interrupt is pending
Figure 20-8. Operations for Slave/Transmitter Mode
20-9
S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
START Slave Rx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS(the received slave address) N
Matched? Y
The IIC address match interrupt is generated
Read IICDS
Clear pending bit to resume. Y
Stop? N
SDA is shifted to IICDS
END
Interrupt is pending
Figure 20-9. Operations for Slave / Receiver Mode
20-10
S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
IIC-BUS INTERFACE SPECIAL REGISTERS
MULTI-MASTER IIC-BUS CONTROL REGISTER (IICCON) Register IICCON Address 0x15400000 R/W R/W Description IIC-Bus control register Reset Value 0000_XXXX
IICCON Acknowledge enable (1)
Bit [7]
Description IIC-bus acknowledge enable bit. 0=Disable ACK generation 1=Enable ACK generation In Tx mode, the IICSDA is free in the ack time. In Rx mode, the IICSDA is L in the ack time.
Initial State 0
Tx clock source selection Tx/Rx Interrupt enable (5) Interrupt pending flag (2) (3)
[6]
Source clock of IIC-bus transmit clock prescaler selection bit. 0= IICCLK = fPCLK /16 1= IICCLK = fPCLK /512 IIC-Bus Tx/Rx interrupt enable/disable bit. 0=Disable interrupt, 1=Enable interrupt IIC-bus Tx/Rx interrupt pending flag. Writing 1 is impossible. When this bit is read as 1, the IICSCL is tied to L and the IIC is stopped. To resume the operation, clear this bit as 0. 0 = 1) Read) No interrupt pending 2) Write) Clear pending condition & Resume the operation. 1 = 1) Read) Interrupt is pending 2) Write) N/A
0
[5] [4]
0 0
Transmit clock value (4)
[3:0]
IIC-Bus transmit clock prescaler IIC-Bus transmit clock frequency is determined by this 4-bit prescaler value, according to the following formula: Tx clock = IICCLK/(IICCON[3:0]+1)
Undefined
NOTES: 1. Interfacing with EEPROM, the ack generation may be disabled before reading the last data in order to generate the STOP condition in Rx mode. 2. A IIC-bus interrupt occurs 1)when a 1-byte transmit or receive operation is completed, 2)when a general call or a slave address match occurs, or 3) if bus arbitration fails. 3. To time the setup time of IICSDA before IISSCL rising edge, IICDS has to be written before clearing the IIC interrupt pending bit. 4. IICCLK is determined by IICCON[6]. Tx clock can vary by SCL transition time. When IICCON[6]=0, IICCON[3:0]=0x0 or 0x1 is not available. 5. If the IICON[5]=0, IICON[4] does not operate correctly. So, It is recommended to set IICCON[4]=1, although you does not use the IIC interrupt.
20-11
S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
MULTI-MASTER IIC-BUS CONTROL/STATUS REGISTER (IICSTAT) Register IICSTAT Address 0x15400004 R/W R/W Description IIC-Bus control/status register Reset Value 0000_0000
IICSTAT Mode selection
Bit [7:6]
Description IIC-bus master/slave Tx/Rx mode select bits: 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode IIC-Bus busy signal status bit: 0 = read) IIC-bus not busy. (IIC always senses BUS start/stop condition.) write) IIC-bus STOP signal generation 1 = read) IIC-bus busy write) IIC-bus START signal generation. The data in IICDS will be transferred automatically just after the start signal. Also, the delay to check the start condition is inserted automatically. IIC-bus data output enable/disable bit: 0=Disable Rx/Tx, 1=Enable Rx/Tx IIC-bus arbitration procedure status flag bit: 0 = Bus arbitration successful 1 = Bus arbitration failed during serial I/O IIC-bus address-as-slave status flag bit: 0 = cleared when START/STOP condition was detected. 1 = Received slave address matches the address value in the IICADD. IIC-bus address zero status flag bit: 0 = cleared when START/STOP condition was detected at the SDA/SCL line. 1 = Received slave address is 00000000b IIC-bus last-received bit status flag bit 0 = Last-received bit is 0 (ACK was received). 1 = Last-receive bit is 1 (ACK was not received).
Initial State 0
Busy signal status / START STOP condition
[5]
0
Serial output enable Arbitration status flag Address-as-slave status flag
[4] [3]
0 0
[2]
0
Address zero status flag
[1]
0
Last-received bit status flag
[0]
0
20-12
S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
MULTI-MASTER IIC-BUS ADDRESS REGISTER (IICADD) Register IICADD Address 0x15400008 R/W R/W Description IIC-Bus address register Reset Value XXXX_XXXX
IICADD Slave address
Bit [7:0]
Description 7-bit slave address, latched from the IIC-bus: When serial output enable=0 in the IICSTAT, IICADD is writeenabled. The IICADD value can be read any time, regardless of the current serial output enable bit (IICSTAT) setting. IICADD is used only when the IIC mode is selected to slave receive/transmit mode. Slave address = [7:1] Not mapped = [0]
Initial State XXXX_XXXX
MULTI-MASTER IIC-BUS TRANSMIT/RECEIVE DATA SHIFT REGISTER (IICDS) Register IICDS Address 0x1540000C R/W R/W Description IIC-Bus transmit/receive data shift register Reset Value XXXX_XXXX
IICDS Data shift
Bit [7:0]
Description 8-bit data shift register for IIC-bus Tx/Rx operation: When serial output enable = 1 in the IICSTAT, IICDS is writeenabled. The IICDS value can be read any time, regardless of the current serial output enable bit (IICSTAT) setting NOTE: The bit[0] of the data, which is transferred just after start condition, is determined by the mode selection bit. If the mode selection bit is "receive", the bit will be 1(read). If the mode selection bit is "transmit", the bit will be 0(write).
Initial State XXXX_XXXX
20-13
S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
NOTES
20-14
S3C2400 RISC MICROPROCESSOR
IIS-BUS INTERFACE
21
OVERVIEW FEATURES
IIS-BUS INTERFACE
Many digital audio systems are introduced into the consumer audio market, including compact disc, digital audio tapes, digital sound processors, and digital TV sound. The S3C2400 IIS (Inter-IC Sound) bus interface can be used to implement a CODEC interface to an external 8/16-bit stereo audio CODEC IC for mini-disc and portable applications. It supports the IIS bus data format and MSB-justified data format. IIS bus interface provides DMA transfer mode for FIFO access instead of an interrupt. It can transmit or receive data simultaneously as well as transmit or receive only.
-- IIS, MSB-justified format compatible -- 8/16-bit data per channel -- 16, 32, 48fs (sampling frequency) serial bit clock per channel -- 256, 384fs master clock -- Programmable frequency divider for master clock and CODEC clock -- 32 bytes (2x16) FIFO for transmit and receive -- Normal and DMA transfer mode
21-1
IIS-BUS INTERFACE
S3C2400 RISC MICROPROCESSOR
BLOCK DIAGRAM
ADDR DATA CNTL BRFC
TxFIFO SFTR RxFIFO CHNC SD
IPSR_A PCLK IPSR_B
SCLK SCLKG LRCK
CDCLK
Figure 21-1. IIS-Bus Block Diagram
FUNCTIONAL DESCRIPTIONS
Bus interface, register bank, and state machine (BRFC) - Bus interface logic and FIFO access are controlled by the state machine. 5-bit dual prescaler (IPSR) - One prescaler is used as the master clock generator of the IIS bus interface and the other is used as the external CODEC clock generator. 16-byte FIFOs (TXFIFO, RXFIFO) - In transmit data transfer, data are written to TXFIFO, and, in the receive data transfer, data are read from RXFIFO. Master IISCLK generaor (SCLKG) - In master mode, serial bit clock is generated from the master clock. Channel generator and state machine (CHNC) - IISCLK and IISLRCK are generated and controlled by the channel state machine. 16-bit shift register (SFTR) - Parallel data is shifted to serial data output in the transmit mode, and serial data input is shifted to parallel data in the receive mode.
21-2
S3C2400 RISC MICROPROCESSOR
IIS-BUS INTERFACE
TRANSMIT OR RECEIVE ONLY MODE Normal transfer IIS control register has FIFO ready flag bits for transmit and receive FIFO. When FIFO is ready to transmit data, the FIFO ready flag is set to '1' if transmit FIFO is not empty. If transmit FIFO is empty, FIFO ready flag is set to '0'. When receive FIFO is not full, the FIFO ready flag for receive FIFO is set to '1' ; it indicates that FIFO is ready to receive data. If receive FIFO is full, FIFO ready flag is set to '0'. These flags can determine the time that CPU is to write or read FIFOs. Serial data can be transmitted or received while CPU is accessing transmit and receive FIFOs in this way. DMA TRANSFER In this mode, transmit or receive FIFO access is made by the DMA controller. DMA service request in transmit or receive mode is made by the FIFO ready flag automatically. TRANSMIT AND RECEIVE MODE In this mode, IIS bus interface can transmit and receive data simultaneously.
21-3
IIS-BUS INTERFACE
S3C2400 RISC MICROPROCESSOR
AUDIO SERIAL INTERFACE FORMAT
IIS-BUS FORMAT The IIS bus has four lines, serial data input (IISDI), serial data output (IISDO), left/right channel select (IISLRCK), and serial bit clock (IISCLK); the device generating IISLRCK and IISCLK is the master. Serial data is transmitted in 2's complement with the MSB first. The MSB is transmitted first because the transmitter and receiver may have different word lengths. It is not necessary for the transmitter to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. When the system word length is greater than the transmitter word length, the word is truncated (least significant data bits are set to '0') for data transmission. If the receiver is sent more bits than its word length, the bits after the LSB are ignored. On the other hand, if the receiver is sent fewer bits than its word length, the missing bits are set to zero internally. And so, the MSB has a fixed position, whereas the position of the LSB depends on the word length. The transmitter always sends the MSB of the next word at one clock period after the IISLRCK change. Serial data sent by the transmitter may be synchronized with either the trailing (HIGH to LOW) or the leading (LOW to HIGH) edge of the clock signal. However, the serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is synchronized with the leading edge. The LR channel select line indicates the channel being transmitted. IISLRCK may change either on a trailing or leading edge of the serial clock, but it does not need to be symmetrical. In the slave, this signal is latched on the leading edge of the clock signal. The IISLRCK line changes one clock period before the MSB is transmitted. This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. Furthermore, it enables the receiver to store the previous word and clear the input for the next word. MSB(LEFT) JUSTIFIED MSB / left justified bus has the same lines as the IIS format. It is only different with the IIS bus that transmitter always sends the MSB of the next word when the IISLRCK change.
21-4
S3C2400 RISC MICROPROCESSOR
IIS-BUS INTERFACE
LRCK
LEFT
RIGHT
LEFT
SCLK
MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st)
SD
IIS-BUS FORMAT (N=8 or 16)
LRCK
LEFT
RIGHT
SCLK
MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last)
SD
MSB-JUSTIFIED FORMAT (N=8 or 16)
Figure 21-2. IIS-Bus and MSB(Left)-justified Data Interface Formats SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency (PCLK) can be selected by sampling frequency as shown in Table 21-1. Because PCLK is made by IIS prescaler, the prescaler value and PCLK type(256 or 384fs) should be determined properly. Serial bit clock frequency type (16/32/48fs) can be selected by the serial bit per channel and PCLK as shown in Table 21-2. Table 21-1 CODEC clock (CODECLK = 256 or 384fs) IISLRCK (fs) 8.000 KHz 256fs CODECLK (MHz) 2.0480 384fs 3.0720 4.2336 6.1440 8.4672 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 2.8224 4.0960 5.6448 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 11.025 KHz 16.000 KHz 22.050 KHz 32.000 KHz 44.100 KHz 48.000 KHz 64.000 KHz 88.200 KHz 96.000 KHz
Table 21-2 Usable serial bit clock frequency (IISCLK = 16 or 32 or 48fs) Serial bit per channel Serial clock frequency (IISCLK) @CODECLK=256fs @CODECLK=384fs 16fs, 32fs 16fs, 32fs, 48fs 32fs 32fs, 48fs 8-bit 16-bit
21-5
IIS-BUS INTERFACE
S3C2400 RISC MICROPROCESSOR
IIS-BUS INTERFACE SPECIAL REGISTERS
IIS CONTROL REGISTER (IISCON) Register IISCON Address 0x15508000(Li/HW, Li/W, Bi/W) 0x15508002(Bi/HW) R/W R/W Description IIS control register Reset Value 0x100
IISCON Left/Right channel index (read only) Transmit FIFO ready flag (read only) Receive FIFO ready flag (read only) Transmit DMA service request enable Receive DMA service request enable Transmit channel idle command Receive channel idle command IIS prescaler enable IIS interface enable (start)
Bit [8] [7] [6] [5] [4] [3] 0 = Left channel 1 = Right channel
Description
Initial State 1 0 0 0 0 0
0 = FIFO is not ready (empty) 1 = FIFO is ready (not empty) 0 = FIFO is not ready (full) 1 = FIFO is ready (not full) 0 = Request disable 1 = Request enable 0 = Request disable 1 = Request enable In Idle state the IISLRCK is inactive(pause Tx) 0 = Channel not idle 1 = Channel idle In Idle state the IISLRCK is inactive(pause Rx) 0 = Channel not idle 1 = Channel idle 0 = Prescaler disable 1 = Prescaler enable 0 = IIS disable (stop) 1 = IIS enable (start)
[2]
0
[1] [0]
0 0
NOTES: 1. The IISCON register can be accessed by byte, halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR instructions or char/short int/int type pointer in Little/Big endian mode. 2. (Li/B/HW/W): Access by byte/halfword/word unit when the endian mode is Little. (Bi/B/HW/W): Access by byte/halfword/word unit when the endian mode is Big.
21-6
S3C2400 RISC MICROPROCESSOR
IIS-BUS INTERFACE
IIS MODE REGISTER (IISMOD) Register IISMOD Address 0x15508004(Li/W, Li/HW, Bi/W) 0x15508006(Bi/HW) R/W R/W Description IIS mode register Reset Value 0x0
IISMOD Master/slave mode select Transmit/receive mode select Active level of left/right channel Serial interface format Serial data bit per channel Master clock frequency select Serial bit clock frequency select
Bit [8] [7:6] [5] [4] [3] [2] [1:0]
Description 0 = Master mode (IISLRCK and IISCLK are output mode) 1 = Slave mode (IISLRCK and IISCLK are input mode) 00 = No transfer 10 = Transmit mode 01 = Receive mode 11 = Transmit and receive mode
Initial State 0 00 0 0 0 0 00
0 = Low for left channel (high for right channel) 1 = High for left channel (low for right channel) 0 = IIS compatible format 1 = MSB (Left)-justified format 0 = 8-bit 1 = 16-bit
0 = 256fs 1 = 384fs (fs: sampling frequency) 00 = 16fs 10 = 48fs 01 = 32fs 11 = N/A
NOTES: 1. The IISMOD register can be accessed by halfword and word unit using STRH/STR and LDRH/LDR instructions or short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W): Access by halfword/word unit when the endian mode is Little. (Bi/HW/W): Access by halfword/word unit when the endian mode is Big.
21-7
IIS-BUS INTERFACE
S3C2400 RISC MICROPROCESSOR
IIS PRESCALER REGISTER (IISPSR) Register IISPSR Address 0x15508008(Li/HW, Li/W, Bi/W) 0x1550800A(Bi/HW) R/W R/W Description IIS prescaler register Reset Value 0x0
IISPSR Prescaler control A
Bit [9:5] Data value: 0 - 31
Description
Initial State 0
NOTE: Prescaler A makes the master clock that is used the internal block and division factor is N+1.
Prescaler control B
[4:0]
Data value: 0 - 31
NOTE: Prescaler B makes the master clock that is used the external block and division factor is N+1.
000
NOTES: 1. The IISPSR register can be accessed by byte, halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR instructions or char/short int/int type pointer in Little/Big endian mode. 2. (Li/B/HW/W): Access by byte/halfword/word unit when the endian mode is Little. (Bi/B/HW/W): Access by byte/halfword/word unit when the endian mode is Big.
IIS FIFO CONTROL REGISTER (IISFCON) Register IISFCON Address 0x1550800C(Li/HW, Li/W, Bi/W) 0x1550800E(Bi/HW) R/W R/W Description IIS FIFO interface register Reset Value 0x0
IISFCON Transmit FIFO access mode select Receive FIFO access mode select Transmit FFO enable Receive FIFO enable Transmit FIFO data count (read only) Receive FIFO data count (read only)
Bit [11] [10] [9] [8] [7:4] [3:0]
Description 0 = Normal access mode 1 = DMA access mode 0 = Normal access mode 1 = DMA access mode 0 = FIFO disable 0 = FIFO disable 1 = FIFO enable 1 = FIFO enable
Initial State 0 0 0 0 000 000
Data count value = 0 ~ 8 Data count value = 0 ~ 8
NOTES: 1. The IISFCON register can be accessed by halfword and word unit using STRH/STR and LDRH/LDR instructions or short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W): Access by halfword/word unit when the endian mode is Little. (Bi/HW/W): Access by halfword/word unit when the endian mode is Big.
21-8
S3C2400 RISC MICROPROCESSOR
IIS-BUS INTERFACE
IIS FIFO REGISTER (IISFIF) IIS bus interface contains two 16-byte FIFO for the transmit and receive mode. Each FIFO has 16-width and 8-depth form, which allows the FIFO to handles data by halfword unit regardless of valid data size. Transmit and receive FIFO access is performed through FIFO entry; the address of FENTRY is 0x15508010. Register IISFIF Address 0x15508010(Li/HW) 0x15508012(Bi/HW) R/W R/W Description IIS FIFO register Reset Value 0x0
IISFIF FENTRY
Bit [15:0]
Description Transmit/Receive data for IIS
Initial State 0
NOTES: 1. The IISFIF register can be accessed by halfword and word unit using STRH and LDRH instructions or short int type pointer in Little/Big endian mode. 2. (Li/HW): Access by halfword unit when the endian mode is Little. (Bi/HW): Access by halfword unit when the endian mode is Big.
21-9
IIS-BUS INTERFACE
S3C2400 RISC MICROPROCESSOR
NOTES
21-10
S3C2400 RISC MICROPROCESSOR
IIS-BUS INTERFACE
21
OVERVIEW FEATURES
IIS-BUS INTERFACE
Many digital audio systems are introduced into the consumer audio market, including compact disc, digital audio tapes, digital sound processors, and digital TV sound. The S3C2400 IIS (Inter-IC Sound) bus interface can be used to implement a CODEC interface to an external 8/16-bit stereo audio CODEC IC for mini-disc and portable applications. It supports the IIS bus data format and MSB-justified data format. IIS bus interface provides DMA transfer mode for FIFO access instead of an interrupt. It can transmit or receive data simultaneously as well as transmit or receive only.
-- IIS, MSB-justified format compatible -- 8/16-bit data per channel -- 16, 32, 48fs (sampling frequency) serial bit clock per channel -- 256, 384fs master clock -- Programmable frequency divider for master clock and CODEC clock -- 32 bytes (2x16) FIFO for transmit and receive -- Normal and DMA transfer mode
21-1
IIS-BUS INTERFACE
S3C2400 RISC MICROPROCESSOR
BLOCK DIAGRAM
ADDR DATA CNTL BRFC
TxFIFO SFTR RxFIFO CHNC SD
IPSR_A PCLK IPSR_B
SCLK SCLKG LRCK
CDCLK
Figure 21-1. IIS-Bus Block Diagram
FUNCTIONAL DESCRIPTIONS
Bus interface, register bank, and state machine (BRFC) - Bus interface logic and FIFO access are controlled by the state machine. 5-bit dual prescaler (IPSR) - One prescaler is used as the master clock generator of the IIS bus interface and the other is used as the external CODEC clock generator. 16-byte FIFOs (TXFIFO, RXFIFO) - In transmit data transfer, data are written to TXFIFO, and, in the receive data transfer, data are read from RXFIFO. Master IISCLK generaor (SCLKG) - In master mode, serial bit clock is generated from the master clock. Channel generator and state machine (CHNC) - IISCLK and IISLRCK are generated and controlled by the channel state machine. 16-bit shift register (SFTR) - Parallel data is shifted to serial data output in the transmit mode, and serial data input is shifted to parallel data in the receive mode.
21-2
S3C2400 RISC MICROPROCESSOR
IIS-BUS INTERFACE
TRANSMIT OR RECEIVE ONLY MODE Normal transfer IIS control register has FIFO ready flag bits for transmit and receive FIFO. When FIFO is ready to transmit data, the FIFO ready flag is set to '1' if transmit FIFO is not empty. If transmit FIFO is empty, FIFO ready flag is set to '0'. When receive FIFO is not full, the FIFO ready flag for receive FIFO is set to '1' ; it indicates that FIFO is ready to receive data. If receive FIFO is full, FIFO ready flag is set to '0'. These flags can determine the time that CPU is to write or read FIFOs. Serial data can be transmitted or received while CPU is accessing transmit and receive FIFOs in this way. DMA TRANSFER In this mode, transmit or receive FIFO access is made by the DMA controller. DMA service request in transmit or receive mode is made by the FIFO ready flag automatically. TRANSMIT AND RECEIVE MODE In this mode, IIS bus interface can transmit and receive data simultaneously.
21-3
IIS-BUS INTERFACE
S3C2400 RISC MICROPROCESSOR
AUDIO SERIAL INTERFACE FORMAT
IIS-BUS FORMAT The IIS bus has four lines, serial data input (IISDI), serial data output (IISDO), left/right channel select (IISLRCK), and serial bit clock (IISCLK); the device generating IISLRCK and IISCLK is the master. Serial data is transmitted in 2's complement with the MSB first. The MSB is transmitted first because the transmitter and receiver may have different word lengths. It is not necessary for the transmitter to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. When the system word length is greater than the transmitter word length, the word is truncated (least significant data bits are set to '0') for data transmission. If the receiver is sent more bits than its word length, the bits after the LSB are ignored. On the other hand, if the receiver is sent fewer bits than its word length, the missing bits are set to zero internally. And so, the MSB has a fixed position, whereas the position of the LSB depends on the word length. The transmitter always sends the MSB of the next word at one clock period after the IISLRCK change. Serial data sent by the transmitter may be synchronized with either the trailing (HIGH to LOW) or the leading (LOW to HIGH) edge of the clock signal. However, the serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is synchronized with the leading edge. The LR channel select line indicates the channel being transmitted. IISLRCK may change either on a trailing or leading edge of the serial clock, but it does not need to be symmetrical. In the slave, this signal is latched on the leading edge of the clock signal. The IISLRCK line changes one clock period before the MSB is transmitted. This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. Furthermore, it enables the receiver to store the previous word and clear the input for the next word. MSB(LEFT) JUSTIFIED MSB / left justified bus has the same lines as the IIS format. It is only different with the IIS bus that transmitter always sends the MSB of the next word when the IISLRCK change.
21-4
S3C2400 RISC MICROPROCESSOR
IIS-BUS INTERFACE
LRCK
LEFT
RIGHT
LEFT
SCLK
MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st)
SD
IIS-BUS FORMAT (N=8 or 16)
LRCK
LEFT
RIGHT
SCLK
MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last)
SD
MSB-JUSTIFIED FORMAT (N=8 or 16)
Figure 21-2. IIS-Bus and MSB(Left)-justified Data Interface Formats SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency (PCLK) can be selected by sampling frequency as shown in Table 21-1. Because PCLK is made by IIS prescaler, the prescaler value and PCLK type(256 or 384fs) should be determined properly. Serial bit clock frequency type (16/32/48fs) can be selected by the serial bit per channel and PCLK as shown in Table 21-2. Table 21-1 CODEC clock (CODECLK = 256 or 384fs) IISLRCK (fs) 8.000 KHz 256fs CODECLK (MHz) 2.0480 384fs 3.0720 4.2336 6.1440 8.4672 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 2.8224 4.0960 5.6448 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 11.025 KHz 16.000 KHz 22.050 KHz 32.000 KHz 44.100 KHz 48.000 KHz 64.000 KHz 88.200 KHz 96.000 KHz
Table 21-2 Usable serial bit clock frequency (IISCLK = 16 or 32 or 48fs) Serial bit per channel Serial clock frequency (IISCLK) @CODECLK=256fs @CODECLK=384fs 16fs, 32fs 16fs, 32fs, 48fs 32fs 32fs, 48fs 8-bit 16-bit
21-5
IIS-BUS INTERFACE
S3C2400 RISC MICROPROCESSOR
IIS-BUS INTERFACE SPECIAL REGISTERS
IIS CONTROL REGISTER (IISCON) Register IISCON Address 0x15508000(Li/HW, Li/W, Bi/W) 0x15508002(Bi/HW) R/W R/W Description IIS control register Reset Value 0x100
IISCON Left/Right channel index (read only) Transmit FIFO ready flag (read only) Receive FIFO ready flag (read only) Transmit DMA service request enable Receive DMA service request enable Transmit channel idle command Receive channel idle command IIS prescaler enable IIS interface enable (start)
Bit [8] [7] [6] [5] [4] [3] 0 = Left channel 1 = Right channel
Description
Initial State 1 0 0 0 0 0
0 = FIFO is not ready (empty) 1 = FIFO is ready (not empty) 0 = FIFO is not ready (full) 1 = FIFO is ready (not full) 0 = Request disable 1 = Request enable 0 = Request disable 1 = Request enable In Idle state the IISLRCK is inactive(pause Tx) 0 = Channel not idle 1 = Channel idle In Idle state the IISLRCK is inactive(pause Rx) 0 = Channel not idle 1 = Channel idle 0 = Prescaler disable 1 = Prescaler enable 0 = IIS disable (stop) 1 = IIS enable (start)
[2]
0
[1] [0]
0 0
NOTES: 1. The IISCON register can be accessed by byte, halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR instructions or char/short int/int type pointer in Little/Big endian mode. 2. (Li/B/HW/W): Access by byte/halfword/word unit when the endian mode is Little. (Bi/B/HW/W): Access by byte/halfword/word unit when the endian mode is Big.
21-6
S3C2400 RISC MICROPROCESSOR
IIS-BUS INTERFACE
IIS MODE REGISTER (IISMOD) Register IISMOD Address 0x15508004(Li/W, Li/HW, Bi/W) 0x15508006(Bi/HW) R/W R/W Description IIS mode register Reset Value 0x0
IISMOD Master/slave mode select Transmit/receive mode select Active level of left/right channel Serial interface format Serial data bit per channel Master clock frequency select Serial bit clock frequency select
Bit [8] [7:6] [5] [4] [3] [2] [1:0]
Description 0 = Master mode (IISLRCK and IISCLK are output mode) 1 = Slave mode (IISLRCK and IISCLK are input mode) 00 = No transfer 10 = Transmit mode 01 = Receive mode 11 = Transmit and receive mode
Initial State 0 00 0 0 0 0 00
0 = Low for left channel (high for right channel) 1 = High for left channel (low for right channel) 0 = IIS compatible format 1 = MSB (Left)-justified format 0 = 8-bit 1 = 16-bit
0 = 256fs 1 = 384fs (fs: sampling frequency) 00 = 16fs 10 = 48fs 01 = 32fs 11 = N/A
NOTES: 1. The IISMOD register can be accessed by halfword and word unit using STRH/STR and LDRH/LDR instructions or short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W): Access by halfword/word unit when the endian mode is Little. (Bi/HW/W): Access by halfword/word unit when the endian mode is Big.
21-7
IIS-BUS INTERFACE
S3C2400 RISC MICROPROCESSOR
IIS PRESCALER REGISTER (IISPSR) Register IISPSR Address 0x15508008(Li/HW, Li/W, Bi/W) 0x1550800A(Bi/HW) R/W R/W Description IIS prescaler register Reset Value 0x0
IISPSR Prescaler control A
Bit [9:5] Data value: 0 - 31
Description
Initial State 0
NOTE: Prescaler A makes the master clock that is used the internal block and division factor is N+1.
Prescaler control B
[4:0]
Data value: 0 - 31
NOTE: Prescaler B makes the master clock that is used the external block and division factor is N+1.
000
NOTES: 1. The IISPSR register can be accessed by byte, halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR instructions or char/short int/int type pointer in Little/Big endian mode. 2. (Li/B/HW/W): Access by byte/halfword/word unit when the endian mode is Little. (Bi/B/HW/W): Access by byte/halfword/word unit when the endian mode is Big.
IIS FIFO CONTROL REGISTER (IISFCON) Register IISFCON Address 0x1550800C(Li/HW, Li/W, Bi/W) 0x1550800E(Bi/HW) R/W R/W Description IIS FIFO interface register Reset Value 0x0
IISFCON Transmit FIFO access mode select Receive FIFO access mode select Transmit FFO enable Receive FIFO enable Transmit FIFO data count (read only) Receive FIFO data count (read only)
Bit [11] [10] [9] [8] [7:4] [3:0]
Description 0 = Normal access mode 1 = DMA access mode 0 = Normal access mode 1 = DMA access mode 0 = FIFO disable 0 = FIFO disable 1 = FIFO enable 1 = FIFO enable
Initial State 0 0 0 0 000 000
Data count value = 0 ~ 8 Data count value = 0 ~ 8
NOTES: 1. The IISFCON register can be accessed by halfword and word unit using STRH/STR and LDRH/LDR instructions or short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W): Access by halfword/word unit when the endian mode is Little. (Bi/HW/W): Access by halfword/word unit when the endian mode is Big.
21-8
S3C2400 RISC MICROPROCESSOR
IIS-BUS INTERFACE
IIS FIFO REGISTER (IISFIF) IIS bus interface contains two 16-byte FIFO for the transmit and receive mode. Each FIFO has 16-width and 8-depth form, which allows the FIFO to handles data by halfword unit regardless of valid data size. Transmit and receive FIFO access is performed through FIFO entry; the address of FENTRY is 0x15508010. Register IISFIF Address 0x15508010(Li/HW) 0x15508012(Bi/HW) R/W R/W Description IIS FIFO register Reset Value 0x0
IISFIF FENTRY
Bit [15:0]
Description Transmit/Receive data for IIS
Initial State 0
NOTES: 1. The IISFIF register can be accessed by halfword and word unit using STRH and LDRH instructions or short int type pointer in Little/Big endian mode. 2. (Li/HW): Access by halfword unit when the endian mode is Little. (Bi/HW): Access by halfword unit when the endian mode is Big.
21-9
IIS-BUS INTERFACE
S3C2400 RISC MICROPROCESSOR
NOTES
21-10
S3C2400 RISC MICROPROCESSOR
SPI INTERFACE
22
OVERVIEW
FEATURES
SPI INTERFACE
The S3C2400 Serial Peripheral Interface(SPI) can interface the serial data transfer. There are two 8bit shift register for transmission and receiving, respectively. During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially) 8bit serial data at a frequency determined by its corresponding control register settings. If you want only to transmit, you may treat the received data as dummy. Otherwise, if you want only to receive, you should transmit dummy '1' data. There are 4 I/O pin signals associated with SPI transfers: the SCK, the MISO data line, the MOSI data line, and the active low /SS pin.
-- SPI Protocol (ver 2.11) compatible -- 8-bit Shift Register for transmit -- 8-bit Shift Register for receive -- 8-bit Prescaler logic -- Polling, Interrupt, and DMA transfer mode
22-1
S3C2400 RISC MICROPROCESSOR
SPI INTERFACE
BLOCK DIAGRAM
Data Bus
LSB 8
MSB S M M S
SPI MISO MISO
Tx 8bit Shift Reg MSB 8 Rx 8bit Shift Reg LSB
SPI MOSI Pin Control Logic MOSI
PCLK
SPI CLK SCK
Prescaler Register Clock SPI Clock (Master) 8bit Prescaler
CLOCK Logic
S M Out In
nSS /SS
Status Register DCOL MULF REDY
CPOL CPHA
APB I/F (INT DMA)
MSTR
INT
REQ
ACK
Figure 22-1. SPI Block Diagram
22-2
S3C2400 RISC MICROPROCESSOR
SPI INTERFACE
SPI OPERATION
Using the SPI interface, 8-bit data can be sending and receiving data simultaneously with an external device. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. The transmission frequency is controlled by making the appropriate bit settings to the SPPRE register when SPI is a master. You can modify its frequency to adjust the baud rate data register value. When SPI is a slave, other master supply the clock. When a programmer writes byte data to SPTDAT register, SPI transmit and receive operation will start simultaneously. Programming Procedure When a byte data is written into the SPTDAT register, SPI starts to transmit if the SPCON's SPE bit & MSTR bit are set. There is a typical programming procedure to operate an SPI card. To program the SPI modules, follow these basic steps: 1. 2. 3. 4. 5. 6. 7. 8. Set Baud Rate Prescaler Register (SPPRE) Set SPCON & SPPIN to configure properly the SPI module Write data 0xFF to SPTDAT 10 times in order to initialize the card Set SPPIN's nCS bit(to '0') to activate the SPI card. Tx data confirm Transfer Ready flag (REDY) to set, and then write data to SPTDAT. Rx data(1): SPCON's TAGD bit disable = normal mode write 0xFF to SPTDAT, then confirm REDY to set, and then read data from Read Buffer Rx data(2): SPCON's TAGD bit enable = Tx Auto Garbage Data mode confirm REDY to set, and then read data from Read Buffer (then automatically start to transfer) Reset SPPIN's nCS (to '1') to deactivate SPI card.
22-3
S3C2400 RISC MICROPROCESSOR
SPI INTERFACE
SPI Transfer Format S3C2400X01 supports 4 different format to transfer the data. Four waveforms are shown for SPICLK.
Figure 22-2. SPI Transfer Format
22-4
S3C2400 RISC MICROPROCESSOR
SPI INTERFACE
Steps for Transmit by DMA 1. 2. 3. 4. 5. 6. 7. The SPI is configured as DMA mode. DMA is configured properly. The SPI requests DMA service. DMA transmits 1byte data to the SPI. The SPI transmits the data to card. Go to step 3 until DMA count is 0. The SPI is configured as interrupt or polling mode with SMOD bits.
Steps for Receive by DMA 1. 2. 3. 4. 5. 6. 7. 8. 9. The SPI is configured as DMA start with SMOD bits and setting TAGD bit. DMA is configured properly. The SPI receives 1byte data from card. The SPI requests DMA service. DMA receives the data from the SPI. Write data 0xFF automatically to SPTDAT. Go to step 4 until DMA count is 0. The SPI is configured as polling mode with SMOD bits and clearing TAGD bit. If SPSTA REDY flag is set, then read the last byte data.
Total received data = DMA TC values + The last data in polling mode(step 9). First DMA received data is dummy, so user can neglect that.
NOTE:
22-5
S3C2400 RISC MICROPROCESSOR
SPI INTERFACE
SPI SPECIAL REGISTERS
SPI CONTROL REGISTER(SPCON) Register SPCON SPCON SPI Mode Select (SMOD) Address 0x15900000 Bit [6:5] R/W R/W Description SPI Control Register Description Determines how and by what SPTDAT is read/written 00 = polling mode, 10 = DMA mode, [4] [3] 01 = interrupt mode 11 = reserved 0 0 Reset Value 0x00 Initial State 00
Prescaler Enable (ENPRE) Master/Slave Select (MSTR)
Determines what you want Prescaler enable or not(only master) 0 = disable, 1 = enable Determines what mode you want master or slave. 0 = slave, 1 = master
NOTE: In slave mode there should be set up time for master to initiate Tx / Rx.
Clock Polarity Select (CPOL) Clock Phase Select (CPHA) Tx Auto Garbage Data mode enable (TAGD)
[2] [1]
Determines an active high or active low clock. 0 = active high, 1 = active low This bit selects one of two fundamentally different transfer formats. 0 = format A, 1 = format B This bit decides whether the receiving data only needs or not. When this bit is normal mode and you only want to receive data, you should transmit dummy 0xFF data. 0 = normal mode, 1 = Tx auto garbage data mode
0 0
[0]
0
22-6
S3C2400 RISC MICROPROCESSOR
SPI INTERFACE
SPI STATUS REGISTER (SPSTA) Register SPSTA SPSTA Reserved Data Collision Error Flag (DCOL) Address 0x15900004 Bit [7:3] [2] This flag is set if the SPTDAT is written or the SPRDAT is read while a transfer is in progress and cleared by reading the SPSTA with DCOL set. 0 = not detect, Multi Master Error Flag (MULF) [1] 1 = collision error detect 0 0 R/W R Description SPI Status Register Description Reset Value 0x01 Initial State
This flag is set if the nSS signal goes to active low while the SPI is configured as a master, and SPPIN's ENMUL bit is multi master errors detect mode. MULF is cleared by reading SPSTA with MULF set. 0 = not detect, 1 = multi master error detect
Transfer Ready Flag (REDY)
[0]
This bit indicates that SPT(R)DAT is ready to transmit or receive. This flag is automatically resetted by writing data to SPTDAT. Initial value is high. 0 = not ready, 1 = data Tx/Rx ready
1
22-7
S3C2400 RISC MICROPROCESSOR
SPI INTERFACE
SPI PIN CONTROL REGISTER (SPPIN) When the SPI system is enabled, the direction of pin is controlled by SPCON's MSTR bit except /SS pin. The direction and usage of /SS pin is controlled by the SPPIN's ENMUL bit when the SPI system is a master. Otherwise, when the SPI system is a slave, /SS pin is always used input for slave select by one master. Register SPPIN SPPIN Reserved Multi Master error detect Enable (ENMUL) Address 0x15900008 Bit [7:3] [2] The /SS pin is used as an input to detect multi master error when the SPI system is a master, regardless the SPPIN's nCS bit. 0 = disable(general purpose) 1 = multi master error detect enable SPI Card Select(nCS) [1] The /SS pin is used as an output to select an SPI card when the SPI system is a master. If SPPIN's EMUL bit is enable, this bit ignores. 0 = card select, Master Out Keep(KEEP) [0] 1 = not select 0 1 0 R/W R/W Description SPI Pin Control Register Description Reset Value 0x02 Initial State
Determines MOSI drive or release when 1byte transmit finish(only master) 0 = release, 1 = drive the previous level
The SPIMISO (MISO) and SPIMOSI (MOSI) data pins are used for transmitting and receiving serial data. When the SPI is configured as a master, SPIMISO (MISO) is the master data input line, SPIMOSI (MOSI) is the master data output line, and SPICLK (SCK) is the clock output line. When as a slave, these pins reverse roles. In a multiplemaster system, all SPICLK (SCK) pins are tied together, all SPIMOSI(MOSI) pins are tied together, and all SPIMISO (MISO) pins are tied together. Only an SPI master can experience a multi master error, caused when a second SPI device becomes a master and selects this device as if it were a slave. When this type error is detected, the following action are taken immediately. But you must previously set SPPIN's ENMUL bit if you want to detect this error. 1. 2. The SPCON's MSTR bit is forced to 0 to operate slave mode. The SPSTA's MULF flag is set, and an SPI interrupt is generated.
22-8
S3C2400 RISC MICROPROCESSOR
SPI INTERFACE
SPI BAUD RATE PRESCALER REGISTER (SPPRE) Register SPPRE SPPRE Prescaler Value Address 0x1590000C Bit [7:0] R/W R/W Description SPI Baud Rate Prescaler Register Description Determines SPI clock rate as above equation. Baud rate = PCLK / 2 / (Prescaler value + 1)
NOTE: Baud rate should be less than 25MHz.
Reset Value 0x00 Initial State 0x00
SPI TX DATA REGISTER (SPTDAT) Register SPTDAT SPTDAT Tx Data Register Address 0x15900010 Bit [7:0] R/W R/W Description SPI Tx Data Register Description This field contains the data to be transmitted over the SPI channel Reset Value 0x00 Initial State 0x00
SPI RX DATA REGISTER(SPRDAT) Register SPRDAT SPRDAT Rx Data Register Address 0x15900014 Bit [7:0] R/W R Description SPI Rx Data Register Description This field contains the data to be received over the SPI channel Reset Value 0x00 Initial State 0x00
22-9
S3C2400 RISC MICROPROCESSOR
SPI INTERFACE
NOTES
22-10
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
23
Symbol VDD VIN VOUT IIN TSTG
ELECTRICAL DATA
ABSOLUTE MAXIMUM RATINGS
Table 23-1. Absolute Maximum Rating Parameter DC Supply Voltage DC Input Voltage DC Input Voltage DC Input Current Storage Temperature 3.3 V Input buffer 3.3 V Output buffer 200 - 65 to 150 Rating 3.8 3.8 3.8 mA
o
Unit
V
C
RECOMMENDED OPERATING CONDITIONS
Table 23-2. Recommended Operating Conditions Symbol VDD VIN VOUT TOPR Parameter DC Supply Voltage for I/O Block DC Supply Voltage for Analog Core DC Input Voltage DC Output Voltage Operating Temperature 3.3V VDD 3.3V VDD 3.3V Input buffer 3.3V Output buffer Commercial Rating 3.30.3 3.30.5% 3.30.3 3.30.3 0 to 70
o
Unit
V
C
23-1
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
D.C. ELECTRICAL CHARACTERISTICS
The following tables define the DC electrical characteristics for the standard LVCMOS I/O buffers. Table 23-3. Normal I/O PAD DC Electrical Characteristics (V DD = 3.3V 0.3V, TA = -40 to 85 C) Symbol VIH Parameters High level input voltage LVCMOS interface VIL Low level input voltage LVCMOS interface VT VT+ VTIIH Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current Input buffer Input buffer with pull-up IIL Low level input current Input buffer Input buffer with pull-up VOH High level output voltage Type B8 Type B12 VOL Low level output voltage Type B8 Type B12 IDS
I DD
Condition
Min
Type
Max
Unit V
2.0 V 0.8 1.4 CMOS CMOS 0.8 2.0 V V
VIN = VDD
-10 10 33
10 60
A
VIN = VSS
-10 -60 -33
10 -10
A
IOH= -8 mA IOH = -12 mA
V 2.4
IOL = 8 mA IOL = 12 mA VIN = VSS or VDD TBD
(note)
V 0.4 A @25 C TBD
(note)
Stop current
Operating current
TBD -- To be Determined.
mA/MHz
NOTE:
23-2
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
Table 23-4. USB DC Electrical Characteristics Symbol VIH VIL IIH IIL VOH VOL Parameter High level input voltage Low level input voltage High level input current Low level input current Static Output High Static Output Low Vin = 3.3V Vin = 0.0V 15Kohm to GND 1.5Kohm to 3.6V -10 -10 2.8 Condition Min 2.5 0.8 10 10 3.6 0.3 Max Unit V V A A V V
23-3
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
A.C. ELECTRICAL CHARACTERISTICS
tXTALCYC
1/2 VDD
1/2 VDD
NOTE:
The clock input from the XTIpll pin.
Figure 23-1. XTIpll Clock Timing
tEXTCYC tEXTHIGH tEXTLOW
1/2 VDD
VIH
VIH VIL VIL
VIH 1/2 VDD
NOTE:
The clock input from the EXTCLK pin.
Figure 23-2. EXTCLK Clock Input Timing
23-4
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
EXTCLK tEX2CK SCLK
tEX2SCK tSCK2CK
CLKOUT (HCLK)
Figure 23-3. EXTCLK/CLKOUT/SCLK in the case that EXTCLK is used without the PLL
HCLK (internal) tHC2CK
SCLK tHC2SCK tSCK2CK CLKOUT (HCLK)
Figure 23-4. HCLK/CLKOUT/SCLK in the case that EXTCLK is used with the PLL
EXTCLK
nRESET
tRESW
tMDRH
OM[3:0]
Figure 23-5. Manual Reset and OM[3:0] Input Timing
23-5
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
Power PLL can operate after OM[3:2] is latched.
nRESET
XTIpll or EXTCLK
...
PLL is configured by S/W first time. tOSC1 VCO is adapted to new clock frequency.
Clock Disable
VCO output
... tRST2RU N ...
FCLK MCU operates by XTIpll or EXTCLK clcok. FCLK is new frequency.
Figure 23-6. Power-On Oscillation Setting Timing
23-6
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
EXTCLK
XTIpll
Clock Disable
tOSC2
VCO Output Several slow clocks (XTIpll or EXTCLK) FCLK
STOP mode is initiated.
Figure 23-7. STOP Mode Return Oscillation Setting Timing
23-7
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
tRAD
tRCD
tRAD
tROD
tRDS
tRAD
tRDS
tRAD
tRDS
tRAD
tRDS
tRDS
tRAD
tRDS
tRAD
tRAD
tRDS
tRAD
tRCD
tROD
Tacc
EXTCLK
nGCSx
ADDR
'1'
tRDS
Figure 23-8. ROM/SRAM Burst READ Timing(I) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=0, DW=16bit)
23-8
DATA
nBEx
nOE
tRDH
tRDH
tRDH
tRDH
tRDH
tRDH
tRDH
tRDH
EXTCLK tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD
tRAD
S3C2400 RISC MICROPROCESSOR
ADDR tRCD
tRCD
nGCSx tROD
tROD
nOE
Tacc tRBED
tRBED
nBEx
tRDS
tRDS
tRDS
tRDS
tRDS
tRDS
tRDS
tRDS
Figure 23-9. ROM/SRAM Burst READ Timing(II) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=1, DW=16bit) tRDH tRDH tRDH tRDH tRDH tRDH tRDH
DATA tRDH
ELECTRICAL DATA
23-9
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
EXTCLK tHZD ADDR 'HZ' tHZD nGS 'HZ' tHZD nOE 'HZ' tXnBRQS XnBREQ tXnBACKD XnBACK tXnBACKD tXnBRQH
Figure 23-10. External Bus Request in ROM/SRAM Cycle (Tacs=0, Tcos=0, Tacc=8, Toch=0, Tcah=0, PMC=0, ST=0)
23-10
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
EXTCLK tRAD ADDR tRCD nGS Tacs tROD nOE tROD Tcah tRCD tRAD
Tcos Tacc Toch
nBE
'1'
tRDS DATA tRDH
Figure 23-11. ROM/SRAM READ Timing (I) (Tacs=2,Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=0)
23-11
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
EXTCLK tRAD ADDR tRCD nGCSx Tacs tROD nOE tROD Tcah tRCD tRAD
Tcos Tacc tRBED Toch tRBED
nBEx
Tcos Toch tRDS
DATA tRDH
Figure 23-12. ROM/SRAM READ Timing (II) (Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2cycle, PMC=0, ST=1)
23-12
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
EXTCLK tRAD ADDR tRCD nGCSx Tacs Tcah tRWD nWE tRWD tRCD tRAD
Tcos Tacc tRWBED Toch tRWBED
nBEx
Tcos Toch tRDD tRDD
DATA
Figure 23-13. ROM/SRAM WRITE Timing (I) (Tacs=2,Tcos=2,Tacc=4,Toch=2, Tcah=2, PMC=0, ST=0)
23-13
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
EXTCLK tRAD ADDR tRCD nGCSx Tacs Tcah tRWD nWE tRWD tRCD tRAD
Tcos Tacc Toch tRBED
tRBED nBEx Tcos
Toch tRDD DATA tRDD
Figure 23-14. ROM/SRAM WRITE Timing (II) (Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=1)
23-14
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
EXTCLK tRC ADDR
nGCSx Tacs nOE Tacc = 6cycle Tacs sampling nWait nWait delayed
DATA
NOTE : The status of nWait is checked at (Tacc-1) cycle.
Figure 23-15. External nWAIT READ Timing (Tacs=0, Tcos=0, Tacc=6, Toch=0, Tcah=0, PMC=0, ST=0)
23-15
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
EXTCLK
ADDR
nGCSx Tacc >= 2cycle nWE tWH tWS nWait
tRDD DATA
tRDD
Figure 23-16. External nWAIT WRITE Timing (Tacs=0, Tcos=0, Tacc=4, Toch=0, Tcah=0, PMC=0, ST=0)
23-16
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
Tcas
Tcp
Tcas
Tcp
Tcas Tcp
Tcas Tcp
Tcas
Tcp
Tcas
Tcp
Tcas
Tcp
tDRD
tDAD
Trcd
EXTCLK
nRASx
nCASx
ADDR
tDOD
Tcas Tcp
tDRCD
tDDS
Figure 23-17. DRAM (EDO) Burst READ Timing (Trcd=2, Tcas=1, Tcp=1, Trp=3.5, MT=10, DW = 16bit)
DATA
nOE
tDDH
23-17
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
EXTCLK tHZD ADDR 'HZ' tHZD nRASx 'HZ' tHZD nCASx
'HZ' tHZD
nOE tXnBRQS XnBREQ tXnBRQL
'HZ' tXnBRQH
tXnBACKD XnBACK
tXnBACKD
Figure 23-18. External Bus Request in DRAM Cycle (Trcd=3, Tcas=2, Tcp=1, Trp=4.5)
23-18
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
EXTCLK tDAD ADDR tDRD nRASx Trcd nCASx tDOD nOE Tcas Tcp tDRCD tDRCD Trp tDRD tDAD tDAD
tDOD
tDDS DATA tDDH
Figure 23-19. DRAM(FP) Single READ Timing (Trcd=3, Tcas=2, Tcp=1, Trp=4.5, MT=01)
23-19
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
EXTCLK tDAD ADDR tDRD nRASx Trcd nCASx tDOD nOE Tcas Tcp Trp tDRD tDAD tDAD
tDRCD
tDRCD
tDOD
tDDS DATA tDDH
Figure 23-20. DRAM(EDO) Single READ Timing (Trcd=3, Tcas=2, Tcp=1, Trp=4.5, MT=10)
23-20
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
EXTCLK
ADDR tDRD nRASx Trp tDCCD nCASx Tchr nOE/nWE '1' tDCCD tDRD
Figure 23-21. DRAM CBR Refresh Timing (Tchr=4)
23-21
23-22
tDAD tDAD tDAD tDAD tDAD tDAD tDRD tDRD tDRD Trp tDRCD tDRCD tDRCD tDRCD tDRCD tDRCD Trcd tDRCD Tcas Tcp Tcp Tcas Tcas tDDS tDDS tDDS
ELECTRICAL DATA
EXTCLK
tDAD
ADDR
nRASx
Trcd
nCASx
tDOD
nOE
DATA tDDH tDDH tDDH
Figure 23-22. DRAM(EDO) Page Hit-Miss READ Timing (Trcd=2, Tcas=2, Tcp=1, Trp=3.5, MT=10)
S3C2400 RISC MICROPROCESSOR
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
EXTCLK
ADDR tDRD nRASx Trp tDCCD nCASx tDCCD tDRD
Figure 23-23. DRAM Self Refresh Timing
EXTCLK tDAD ADDR tDRD nRASx Trcd nCASx tDWD nWE Tcas Tcp Trp tDRD tDAD tDAD
tDWCD
tDWCD
tDWD
tDDD DATA
tDDD
Figure 23-24. DRAM(FP/EDO) Single Write Timing (Trcd=3, Tcas=2, Tcp=1, Trp=4.5, MT=01/10)
23-23
23-24
tDAD tDAD tDAD tDAD tDAD tDAD tDRD tDRD Trp tDWCD tDWCD tDWCD tDWCD tDWCD tDWCD Trcd tDWCD Tcas Tcp Tcp Tcas Tcas tDDD tDDD tDDD
ELECTRICAL DATA
EXTCLK
tDAD
ADDR
tDRD
nRASx
Trcd
nCASx
tDWD
nWE
tDDD
Figure 23-25. DRAM(FP/EDO) Page Hit-Miss Write Timing (Trcd=2, Tcas=2, Tcp=1, Trp=3.5, MT=01/10)
S3C2400 RISC MICROPROCESSOR
DATA
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
EXTCLK tRAD ADDR tRCD nGCSx Tacs tROD nOE tRAD
Tcos Tacc tRDS
DATA tRDH
Figure 23-26. Masked-ROM Single READ Timing (Tacs=2, Tcos=2, Tacc=8, PMC=01/10/11)
EXTCLK tRAD ADDR tRCD nGCSx tRAD tRAD tRAD tRAD tRAD
tROD nOE Tacc Tpac tRDS DATA tRDH tRDH tRDH tRDH tRDH Tpac tRDS tRDS Tpac Tpac tRDS tRDS
Figure 23-27. Masked-ROM Consecutive READ Timing (Tacs=0, Tcos=0, Tacc=3, Tpac=2, PMC=01/10/11)
23-25
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
tSCSD
Trp
Trcd
tSBED
tSCD
Tcl
tSAD
'1'
tSAD
ADDR/BA
A10/AP
tSRD
nSRAS
nSCAS
nGCSx
SCKE
tSWD
tSDS
Figure 23-28. SDRAM Single Burst READ Timing (Trp=2, Trcd=2, Tcl=2, DW=16bit)
23-26
DATA
SCLK
nBEx
nWE
tSDH
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
EXTCLK tHZD SCLK 'HZ'
tHZD
SCKE
'1'
tHZD
'HZ'
ADDR/BA 'HZ' tHZD
A10/AP tHZD
'HZ'
nGCSx tHZD
'HZ'
nSRAS tHZD
'HZ'
nSCAS tHZD 'HZ'
nBEx tHZD
'HZ'
nWE 'HZ' tXnBRQS XnBREQ tXnBRQL tXnBRQH
XnBACK tXnBACKD tXnBACKD
Figure 23-29. External Bus Request in SDRAM Timing (Trp=2, Trcd=2, Tcl=2)
23-27
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
SCLK
SCKE
'1' tSAD tSAD
ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD
tSRD nSRAS
tSRD
tSCD nSCAS
nBEx
'1'
tSWD nWE
tSWD
DATA
'HZ'
Figure 23-30. SDRAM MRS Timing
23-28
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
SCLK
SCKE
'1' tSAD tSAD tSAD tSAD
ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD tSCSD tSAD
tSRD nSRAS Trp
tSRD
Trcd tSCD
nSCAS
tSBED nBEx Tcl tSWD nWE
tSDS DATA tSDH
Figure 23-31. SDRAM Single READ Timing(I) (Trp=2, Trcd=2, Tcl=2)
23-29
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
SCLK
SCKE
'1' tSAD tSAD tSAD tSAD
ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD tSCSD tSAD
tSRD nSRAS Trp
tSRD
Trcd tSCD
nSCAS
tSBED nBEx Tcl tSWD nWE
tSDS DATA tSDH
Figure 23-32. SDRAM Single READ Timing(II) (Trp=2, Trcd=2, Tcl=3)
23-30
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
SCLK
SCKE
'1' tSAD tSAD
ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD
tSRD nSRAS Trp
tSRD
'1' Trc tSCD
nSCAS
nBEx
'1'
tSWD nWE
DATA
'HZ'
NOTE:
Before executing auto/self refresh command, all banks must be idle state.
Figure 23-33. SDRAM Auto Refresh Timing (Trp=2, Trc=4)
23-31
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
Tcl
tSCSD
Trp
Trcd
tSBED
tSCD
Tcl
tSAD
'1'
tSAD
ADDR/BA
A10/AP
tSRD
nSRAS
nSCAS
nGCSx
SCKE
tSWD
Tcl
tSDS
Figure 23-34. SDRAM Page Hit-Miss READ Timing (Trp=2, Trcd=2, Tcl=2)
23-32
DATA
SCLK
nBEx
nWE
tSDH
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
SCLK tCKED SCKE tSAD ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD '1' tSAD tCKED
tSRD nSRAS Trp
tSRD '1' Trc
'1' tSCD
nSCAS
'1'
nBEx
'1' tSWD
'1'
nWE
'1'
DATA
'HZ'
'HZ'
NOTE:
Before executing auto/self refresh command, all banks must be idle state.
Figure 23-35. SDRAM Self Refresh Timing (Trp=2, Trc=4)
23-33
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
SCLK
SCKE
'1' tSAD tSAD tSAD tSAD
ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD tSCSD tSAD
tSRD nSRAS Trp
tSRD
Trcd tSCD
nSCAS
tSBED nBEx
tSWD nWE
tSDD DATA tSDD
Figure 23-36. SDRAM Single Write Timing (Trp=2, Trcd=2)
23-34
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
tSBED
tSCD
tSCSD
Trp
Trcd
'1'
tSAD
ADDR/BA
tSAD
nGCSx
A10/AP
tSRD
nSRAS
nSCAS
SCKE
SCLK
tSWD
tSDD
Figure 23-37. SDRAM Page Hit-Miss Write Timing (Trp=2, Trcd=2, Tcl=2)
DATA
nBEx
nWE
tSDD 23-35
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
XSCLK tXRS XnXDREQ tXAD XnXDACK
Read Write
tXRS tCADH
Min. 3MCLK tCADL
Figure 23-38. External DMA Timing (Handshake, Single transfer)
T2 T1 VFRAME VM VLINE VCLK Expanded View First Line Check & Data Timing VFRAME VM VLINE VCLK VD[7:0] Tc2dhold Tl2c Tc2dsetup Tcwidth
Figure 23-39. STN LCD Controller Timing
23-36
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
Tf2hsetup VSYNC Tf2hhold HSYNC Tvfpd
Tvspw VDEN
Tvbpd
HSYNC Tl2csetup VCLK Tvclkl VD Tvdsetup VDEN Tle2chold LEND Tlewidth Tve2hold Tvdhold Tvclkh Tvclk
Figure 23-40. TFT LCD Controller Timing
23-37
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
MMCCLK
MMCCM
tCMDS
tCMDH
MMCDA
tDATS
tDATH
Figure 23-41. MMC Interface Receive Timing
SPICLK
SPIMISO
tMISOS
tMISOH
SPIMOSI (Slave)
tMOSIS
tMOSIH
Figure 23-42. SPI Interface Receive Timing
23-38
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
Table 23-5. Clock Timing Constants (V DDP = 3.3V, VDDI = 1.8V, TA = 25 C, max/min = typ 30%) Parameter Crystal clock input frequency Crystal clock input cycle time External clock input frequency External clock input cycle time External clock input low level pulse width External clock to CLKOUT (without PLL) External clock to SCLK (without PLL) HCLK(internal) to CLKOUT (with PLL) HCLK(internal) to SCLK (with PLL) SCLK to CKOUT External clock input high level pulse width Mode reset hold time Reset assert time after clock stabilization Power-on oscillation setting time STOP mode return oscillation setting time the interval before CPU runs after nRESET is released. Symbol fXTAL tXTALCYC fEXT tEXTCYC tEXTLOW tEX2CK tEX2SCLK tHC2CK tHC2SCLK tSCLK2CK tEXTHIGH tMDRH tRESW tOSC1 tOSC2 tRST2RUN Min 6 50 1 15.1 5 - - - - - 5 3.0 4 - - - Typ - - - - - 14 9.1 7.7 2.8 4.9 - - - - - 7 Max 20 166.7 66 1000 - - - - - - - - - 4096 4096 - Unit MHz ns MHz ns ns ns ns ns ns ns ns ns XTIpll or EXTCLK XTIpll or EXTCLK XTIpll or EXTCLK XTIpll or EXTCLK
23-39
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
Table 23-6. ROM/SRAM Bus Timing Constants (V DD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter ROM/SRAM Address Delay ROM/SRAM Chip select Delay ROM/SRAM Output enable Delay ROM/SRAM read Data Setup time. ROM/SRAM read Data Hold time. ROM/SRAM Byte Enable Delay ROM/SRAM Write Byte Enable Delay ROM/SRAM output Data Delay ROM/SRAM external Wait Setup time ROM/SRAM external Wait Hold time ROM/SRAM Write enable Delay Symbol tRAD tRCD tROD tRDS tRDH tRBED tRWBED tRDD tWS tWH tRWD Min - - - - - - - - - - - Typ 13 8 7 1 5 8 8 8 1 5 9 Max - - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns
23-40
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
Table 23-7. Clock Timing Constants (V DD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter DRAM Address Delay DRAM Row active Delay DRAM Read Column active Delay DRAM Output enable Delay DRAM read Data Setup time DRAM read Data Hold time DRAM Write Cas active Delay DRAM Cbr Cas active Delay DRAM Write enable Delay DRAM output Data Delay Symbol tDAD tDRD tDRCD tDOD tDDS tDDH tDWCD tDCCD tDWD tDDD Min - - - - - - - - - - Typ 9 14 15 14 1 5 15 9 15 16 Max - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns
Table 23-8. Memory Interface Timing Constants (V DD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter SDRAM Address Delay SDRAM Chip Select Delay SDRAM Row active Delay SDRAM Column active Delay SDRAM Byte Enable Delay SDRAM Write enable Delay SDRAM read Data Setup time SDRAM read Data Hold time SDRAM output Data Delay SDRAM Clock Eable Delay Symbol tSAD tSCSD tSRD tSCD tSBED tSWD tSDS tSDH tSDD Tcked Min - - - - - - - - - - Typ 5 4 4 4 4 4 4 0 5 5 Max - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns
23-41
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
Table 23-9. External Bus Request Timing Constants (V DD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter eXternal Bus Request Setup time eXternal Bus Request Hold time eXternal Bus Ack Delay HZ Delay Symbol tXnBRQS tXnBRQH tXnBACKD tHZD Min - - - - Typ. 2 5 15 6 Max - - - - Unit ns ns ns ns
Table 23-10. DMA Controller Module Signal Timing Constants (V DD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter eXternal Request Setup aCcess to Ack Delay when Low transition aCcess to Ack Delay when High transition eXternal Request Delay Symbol tXRS tCADL tCADH tXAD Min - - - 2 Typ. 9.3 6.8 6.6 - Max - - - - Unit ns ns ns MCLK
23-42
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
Table 23-11. STN LCD Controller Module Signal Timing Constants (V DD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter VFRAME setup to VLINE falling edge VFRAME hold from VLINE falling edge VLINE falling edge to VCLK rising edge VD setup to VCLK falling edge VD hold from VCLK falling edge VCLK Period
NOTE: HCLK period
Symbol T1 T2 Tl2c Tc2dsetup Tc2dhold Tcwidth
Min 16 16 16 2 2 4
Typ - - - - - -
Max - - - - - -
Units Phclk (note) Phclk Phclk Phclk Phclk Phclk
Table 23-12. TFT LCD Controller Module Signal Timing Constants (V DD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter Vertical sync pulse width Vertical back porch delay Vertical front porch dealy VCLK pulse width VCLK pulse width high VCLK pulse width low Hsync setup to VCLK falling edge VDEN set up to VCLK falling edge VDEN hold from VCLK falling edge VD setup to VCLK falling edge VD hold from VCLK falling edge LEND width LEND hold from VCLK rising edge VSYNC setup to HSYNC falling edge VSYNC hold from HSYNC falling edge
NOTES: 1. HSYNC period 2. VCLK period
Symbol Tvspw Tvbpd Tvfpd Tvclk Tvclkh Tvclkl Tl2csetup Tde2csetup Tde2chold Tvd2csetup Tvd2chold Tlewidth Tle2chold Tf2hsetup Tf2hhold
Min VSPW + 1 VBPD+1 VFPD+1 1 0.5 0.5 0.5 0.5 0.5 0.5 0.5
Typ - - - - - - - - - - - 1
Max - - - - - - - - - - - - - - -
Units Phclk (note1) Phclk Phclk Pvclk (note2) Pvclk Pvclk Pvclk Pvclk Pvclk Pvclk Pvclk Pvclk ns Pvclk Pvclk
3 HSPW + 1 HBPD + HFPD + HOZVAL + 3
- - -
23-43
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
Table 23-13. IIS Controller Module Signal Timing Constants (V DD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter IISLRCK delay time IISDO delay time IISDI input setup time IISDI input hold time CODEC clock frequency Symbol tLRCK tSDO tSDIS tSDIH tCODEC Min 0.5 0.4 7.9 0.3 1/16 Typ. - - - - - Max 5.7 2.5 - - 1 Unit ns ns ns ns fIIS_BLOCK
Table 23-14. IIC BUS Controller Module Signal Timing (V DD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter SCL clock frequency SCL high level pulse width SCL low level pulse width Bus free time between STOP and START START hold time SDA hold time SDA setup time STOP setup time Symbol fSCL tSCLHIGH tSCLLOW tBUF tSTARTS tSDAH tSDAS TstOPH Min - std. 4.0 fast 0.6 std. 4.7 fast 1.3 std. 4.7 fast 1.3 std. 4.0 fast 0.6 std. 0 fast 0 std. 250 fast 100 std. 4.0 fast 0.6 Typ. - - - - - - - - Max std. 100 fast 400 - - - - std. - fast 0.9 - - Unit kHz s s s s s ns s
NOTE: Std. means Standard Mode and fast means Fast Mode.
23-44
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
Table 23-15. MMC Interface Transmit/Receive Timing Constants (V DD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter CMD Receive data input setup time CMD Receive data input hold time DAT Receive data input setup time DAT Receive data input hold time Symbol tCMDS tCMDH tDATS tDATH Min - - - - Typ. 9.1 0.1 8.8 0.1 Max - - - - Unit ns ns ns ns
Table 23-16. SPI Interface Transmit/Receive Timing Constants (V DD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter MISO Receive data input setup time MISO Receive data input hold time MOSI(slave) Receive data input setup time MOSI(slave) Receive data input hold time Symbol tMISOS tMISOH tMOSIS tMOSIH Min - - - - Typ. 9.4 0.1 0.1 0.8 Max - - - - Unit ns ns ns ns
23-45
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
Table 23-17. USB Electrical Specifications (V DD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter Supply Current Suspend Device Leakage Current Hi-Z state Input Leakage Input Levels Differential Input Sensitivity VDI | (D+) - (D-) | 0.2 V Differential Common Mode Range Single Ended Receiver Threshold Output Levels Static Output Low Static Output High Capacitance Transceiver Capacitance CIN Pin to GND 20 pF VOL VOH RL of 1.5Kohm to 3.6V RL of 15Kohm to GND 2.8 0.3 3.6 V VCM VSE Includes VDI range 0.8 0.8 2.5 2.0 ILO 0V < VIN < 3.3V -10 10 A ICCS 10 A Symbol Condition Min Max Unit
Table 23-18. USB Full Speed Output Buffer Electrical Characteristics (V DD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter Driver Characteristics Transition Time Rise Time Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage Drive Output Resistance TR TF TRFM VCRS ZDRV Steady state drive CL = 50pF CL = 50pF (TR / TF ) 4.0 4.0 90 1.3 28 2.0 2.0 110 2.0 43 % V ohm ns Symbol Condition Min Max Unit
23-46
S3C2400 RISC MICROPROCESSOR
ELECTRICAL DATA
Table 23-19. USB Low Speed Output Buffer Electrical Characteristics (V DD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter Driver Characteristics Transition Time Rising Time Falling Time TR TF CL = 50pF CL = 350pF CL = 50pF CL = 350pF Rise/Fall Time Matching Output Signal Crossover Voltage TRFM VCRS (TR / TF ) 80 1.3 75 300 120 2.0 % V 75 300 ns Symbol Condition Min Max Unit
23-47
ELECTRICAL DATA
S3C2400 RISC MICROPROCESSOR
NOTES
23-48
S3C2400 RISC MICROPROCESSOR
MECHANICAL DATA
24
MECHANICAL DATA
PACKAGE DIMENSIONS
30.00 0.30 28.00 0.20 0-8
+ 0.10
0.127- 0.05
28.00 0.20
30.60 0.30
208-LQFP-2828
#208
#1 0.50
+ 0.10
0.20 - 0.05 0.08MAX (1.25)
0.10 0.05 1.40 0.10 1.60MAX
NOTE: Dimensions are in millimeters.
Figure 24-1. 208-LQFP- 2828 Package Dimension
0.50 0.20 0.10MAX
24-1
MECHANICAL DATA
S3C2400 RISC MICROPROCESSOR
Figure 24-2. 208-FBGA-12.0X12.0 Package Dimension 1
24-2
S3C2400 RISC MICROPROCESSOR
MECHANICAL DATA
Figure 24-3. 208-FBGA-12.0X12.0 Package Dimension 2
24-3
MECHANICAL DATA
S3C2400 RISC MICROPROCESSOR
Figure 24-4. 208-FBGA-15.0X15.0 Package Dimension 1
24-4
S3C2400 RISC MICROPROCESSOR
MECHANICAL DATA
Figure 24-5. 208-FBGA-15.0X15.0 Package Dimension 2
24-5
MECHANICAL DATA
S3C2400 RISC MICROPROCESSOR
NOTES
24-6

▲Up To Search▲

Price & Availability of S3C2400

	To Download S3C2400 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .